Oxide Semiconductor Memory Stacked Gate Structure

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Solution Overview

Problem

Current memory devices fail to meet the demands for high operating speed, high storage density, and low bit cost, making them unsuitable for individual intended purposes despite the increasing need for higher capacity and reduced costs in data handling.

Innovation Solution

A semiconductor memory design featuring a stacked gate structure with an oxide semiconductor layer between select transistors, using a gate insulating film and control gate electrodes to manage charge storage and data retention, allowing for efficient data writing and reading without high voltage tunneling, thus reducing degradation and improving data retention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional memory devices are used, then current storage capacity is maintained, but operating speed, storage density, and bit cost requirements cannot be met

Engineering Contradiction:
Improveoperating speedVSAvoiddata retention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the material parameter of the semiconductor layer from conventional silicon-based materials to oxide semiconductor materials (such as In-Ga-Zn-O). This material parameter change enables the memory device to achieve both high operating speed and excellent data retention characteristics, as oxide semiconductors have unique properties including wide bandgap and low defect density that simultaneously improve speed and reliability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite structure combining oxide semiconductor layers with specific gate insulating films and control gate electrodes. This composite material approach creates a memory device that leverages the advantages of each material component to achieve high operating speed while maintaining excellent data retention, resolving the contradiction between speed and reliability

Inventive Principle:
Principle #40Composite materials

2Quantity of substance

If storage density is increased, then capacity demands are met, but bit cost reduction is compromised

Engineering Contradiction:
Improvestorage densityVSAvoidbit cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from planar memory structures to three-dimensional stacked structures with multiple layers including oxide semiconductor layers, gate insulating films, and control gate electrodes stacked vertically. This dimensional change enables significantly higher storage density while maintaining manufacturing efficiency, as the vertical stacking allows more storage cells to be packed into the same footprint without proportionally increasing fabrication complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The oxide semiconductor layer serves multiple functions simultaneously: it acts as the active semiconductor channel, provides charge storage capability, and enables low-voltage operation. This multi-functionality reduces the number of additional components needed, thereby reducing bit cost while achieving high storage density

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Speed

If high voltage tunneling is used for data writing, then data writing speed is improved, but memory cell degradation increases

Engineering Contradiction:
Improvedata writing speedVSAvoidmemory cell degradation
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent replaces the high-voltage tunneling mechanism with a low-voltage field-effect transistor switching mechanism based on oxide semiconductors. Instead of using high voltage to force charge tunneling through barriers, the invention uses controlled electric fields to modulate the conductivity of the oxide semiconductor channel, achieving fast data writing without the damaging high voltage stress that causes memory cell degradation

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

4Reliability

If conventional semiconductor materials are used, then manufacturing process is simple, but data retention and operating speed are insufficient

Engineering Contradiction:
Improvedata retentionVSAvoidsemiconductor layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the fundamental material parameter from conventional silicon-based semiconductors to oxide semiconductors (such as In-Ga-Zn-O). This single material parameter change simultaneously improves data retention due to the wide bandgap and low defect density of oxide semiconductors, and enhances operating speed, while the added structural complexity is offset by the versatility of the oxide semiconductor material

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The semiconductor memory achieves quick data writing and erasure operations, reduces memory cell degradation, and enhances data reliability with improved storage density and reduced bit cost, enabling high-performance memory solutions.

Implementation Method 1

an oxide semiconductor layer disposed above the semiconductor layer between the first and second select transistors via the gate insulating film

Methodology Applied
Scientific EffectCharge storage: Capacitance

Data Source

PatentUS10043808B1Semiconductor memory
Publication Date: 2018.08.07 KIOXIA CORP
  • US10043808B1 patent drawing
  • US10043808B1 patent drawing
  • US10043808B1 patent drawing

AI summary

According to one embodiment, a semiconductor memory includes: a first gate of a first select transistor and a second gate of a second select transistor on a gate insulating film on a semiconductor layer; an oxide semiconductor layer above the semiconductor layer; a first control gate of a first cell and a second control gate of a second cell on an insulating layer on the oxide semiconductor layer; a third gate of a first transistor between the first control gate and the second control gate; a fourth gate of a second transistor between a first end of the oxide semiconductor layer and the second control gate; an interconnect connected to the first end; a source line connected to the first select transistor; and a bit line connected to the second select transistor.