Oxide Semiconductor Layer Structure for High-Density Low-Power Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization, integration, achieving high on-state current, excellent frequency characteristics, and reducing power consumption while maintaining reliable electrical performance and design flexibility.
Innovation Solution
A semiconductor device structure incorporating specific layers of insulators and conductors with varying conductivity levels, including a transistor and capacitor configuration, where the third oxide has a higher conductivity than the second oxide, and the fourth oxide has a higher conductivity than the second oxide, with the fifth oxide in contact with both, enhancing electrical characteristics and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are miniaturized and highly integrated, then device density and functionality are improved, but manufacturing complexity and reliability challenges increase
Solution Approach 1:
The semiconductor device is divided into multiple functional layers including insulator layers (204, 206, 208, 210), oxide layers (230a, 230b, 230c), and conductor layers (247, 242a, 242b, 260a, 260b). Each layer serves specific functions such as insulation, charge trapping, conduction, and gate control, allowing complex functionality to be achieved through modular layering rather than monolithic structures.
Solution Approach 2:
The device employs composite material structures combining different oxide materials (e.g., In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide) with distinct conductivity characteristics. These composite oxide layers are integrated with insulator and conductor materials to create a multi-material system that optimizes electrical performance while managing fabrication complexity through standardized deposition processes.
2Loss of energy
If oxide semiconductor layers are used to achieve low off-state current, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes controlled variations in oxide layer thickness parameters to achieve desired electrical characteristics. Specific thickness ranges are specified for different oxide layers (e.g., channel formation region thickness, gate insulator thickness) to optimize the balance between off-state current suppression and manufacturing feasibility. The layered oxide structure with varying thicknesses allows precise control of electrical properties through parameter optimization rather than requiring extreme manufacturing precision.
Data Source
AI summary
A semiconductor device including: a first insulator in which an opening is formed; a first conductor positioned in the opening; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide and the first conductor; a third conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a fourth conductor positioned over the second insulator and overlapping with the fifth oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide. The second conductor is in contact with the top surface of the first conductor.