Oxide Semiconductor Transistor With Multi-Channel Gate Structure
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Solution Overview
Problem
Miniaturization of transistors leads to deterioration and variation in electrical characteristics, such as negative threshold voltage shift and subthreshold value deterioration, resulting in reduced on-state current and reliability.
Innovation Solution
A semiconductor device with an oxide semiconductor layer featuring multiple channel formation regions and a gate electrode structure that applies an electric field from both side and top surfaces, along with an oxide layer between the oxide semiconductor and insulating layers to prevent trap state formation, enhancing threshold voltage control and on-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a transistor is miniaturized to achieve high integration, then the integration density is improved, but the on-state current and electrical characteristics deteriorate
Solution Approach 1:
The invention transitions from a conventional planar gate structure to a three-dimensional gate structure where the gate electrode extends along the channel width direction. This dimensional change allows the gate to control multiple channel formation regions simultaneously, improving electrical characteristics without requiring further miniaturization, thus resolving the contradiction between integration density and electrical characteristic deterioration
Solution Approach 2:
The channel formation region is divided into multiple parallel regions (first channel formation region and second channel formation region) along the channel width direction. This segmentation increases the total effective channel width while maintaining control over each individual region through the extended gate structure, thereby improving on-state current and electrical characteristics
2Length of moving object
If the channel width is decreased to miniaturize the transistor, then the transistor size is reduced, but the on-state current decreases
Solution Approach 1:
The gate electrode is extended along the channel width direction to create a three-dimensional structure. This allows the gate to control multiple channel formation regions in parallel, effectively increasing the total channel width and on-state current while keeping the footprint of each individual channel region small, thus resolving the contradiction between transistor size and on-state current
Solution Approach 2:
Multiple channel formation regions are merged into a single transistor structure under one extended gate electrode. The gate controls all channel regions simultaneously, combining their current-carrying capabilities to achieve high on-state current in a compact structure
3Productivity
If the transistor is miniaturized, then the device density is improved, but the threshold voltage control and subthreshold value deteriorate
Solution Approach 1:
The gate electrode is extended along the channel width direction to form a three-dimensional structure that provides comprehensive control over multiple channel formation regions. This enhanced gate control improves threshold voltage stability and subthreshold characteristics while maintaining high device density through compact design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents deterioration in electrical characteristics, increases on-state current, and improves reliability by controlling threshold voltage and reducing trap states, thereby addressing the challenges of miniaturization.
Implementation Method 1
a gate electrode layer is provided to cover a side surface and a top surface of each channel formation region with a gate insulating layer provided therebetween. With such a structure, an electric field is applied to each channel formation region from the side surface direction and the top surface direction
Implementation Method 2
When the oxide semiconductor layer is in contact with the insulating layer, a trap state can be formed at the interface between the oxide semiconductor layer and the insulating layer. The above structure including the oxide layer between the oxide semiconductor layer and the insulating layer suppresses formation of the trap state and thus can prevent deterioration of electrical characteristics of a transistor
Data Source
AI summary
The semiconductor device includes an oxide semiconductor layer including a plurality of channel formation regions arranged in the channel width direction and parallel to each other and a gate electrode layer covering a side surface and a top surface of each channel formation region with a gate insulating layer placed between the gate electrode layer and the channel formation regions. With this structure, an electric field is applied to each channel formation region from the side surface direction and the top surface direction. This makes it possible to favorably control the threshold voltage of the transistor and improve the S value thereof. Moreover, with the plurality of channel formation regions, the transistor can have increased effective channel width; thus, a decrease in on-state current can be prevented.