Multi-gate Transistor with Oxide Semiconductor for Low Off-state Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in reducing current flow between the source and drain when the gate voltage is 0 V, achieving stable operation at high temperatures, and minimizing power consumption while maintaining reliable high-voltage driving capabilities.
Innovation Solution
A multi-gate transistor structure is implemented, combining a single-gate and dual-gate transistor in series, utilizing an oxide semiconductor film with specific gate insulating films and conductive films to control the gate voltage and channel length, thereby reducing off-state current and increasing on-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional single-gate transistor is used, then the device structure is simple, but the off-state current is high and power consumption increases
Solution Approach 1:
The transistor channel is divided into two separate regions, each controlled by an independent gate electrode (first gate and second gate). This segmentation allows independent control of different channel portions, enabling the channel to be completely pinched off at both interfaces when either gate is at 0V, thereby reducing off-state current and power consumption while maintaining a relatively simple overall structure
Solution Approach 2:
The invention transitions from conventional single-gate control to dual-gate control by adding a second gate electrode perpendicular to the first gate. This dimensional extension creates independent control interfaces at both ends of the channel, enabling complete channel depletion and significantly reducing leakage current without excessive structural complexity
2Stability of the object's composition
If the gate voltage is increased to achieve high-temperature stability, then thermal stability improves, but power consumption increases
Solution Approach 1:
The dual-gate structure enables dynamic and flexible voltage control of the channel. By independently adjusting the first and second gate voltages, the channel can be completely pinched off (0V at either gate) to eliminate leakage and reduce power consumption, or fully activated (positive voltage at both gates) to achieve high-temperature stability and high current drive, providing adaptive operation across different temperature and performance requirements
3Loss of energy
If the channel length is increased to reduce current leakage, then off-state current decreases, but on-state current also decreases
Solution Approach 1:
The channel is segmented into two regions controlled by independent gates, allowing each region to be optimized separately. The first gate controls the first channel region while the second gate controls the second channel region, enabling complete depletion at both interfaces to reduce leakage without requiring an excessively long overall channel length, thereby maintaining good on-state current characteristics
Solution Approach 2:
By independently controlling the voltage parameters of the first and second gates, the invention achieves complete channel pinching off (reducing leakage) when either gate is at 0V, or full channel activation (increasing on-state current) when both gates are at positive voltage, providing flexible parameter adjustment to optimize both leakage and drive current
Data Source
AI summary
A semiconductor device with a transistor in which current flowing between a source and a drain when the voltage of a gate electrode is 0 V can be reduced is provided. The semiconductor device incorporates a multi-gate transistor having an oxide semiconductor film formed over an insulating surface, a first gate insulating film in contact with a first surface of the oxide semiconductor film, a first gate electrode between the insulating surface and the oxide semiconductor film, a second gate insulating film in contact with a second surface of the oxide semiconductor film, and a second gate electrode in contact with the second gate insulating film. The oxide semiconductor film has a first region overlapping with the first gate electrode and a second region not overlapping with the first gate electrode, and the second gate electrode overlaps with the first region and the second region of the oxide semiconductor film.