Oxide Semiconductor TFT Multilayer Structure for Leakage Reduction

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Solution Overview

Problem

Oxide semiconductor TFTs with top gate structures face issues of channel-forming region damage during production, leading to increased off-leakage current and unstable characteristics, which is also observed in double-gate TFTs with both top and bottom gates.

Innovation Solution

A semiconductor device with an oxide semiconductor TFT featuring a multilayer structure including a channel oxide semiconductor layer and a protective oxide semiconductor layer, where the channel layer is closer to the substrate, and an upper gate electrode partially overlapping the oxide semiconductor layer, with an interlayer insulating layer covering both, and electrodes in contact with the channel layer through openings in the insulating layer, reducing damage and off-leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a top gate structure is used in oxide semiconductor TFTs, then the mobility and switching speed are improved, but the channel-forming region may be damaged during production processes, leading to increased off-leakage current and unstable characteristics

Engineering Contradiction:
Improveswitching speedVSAvoidcharacteristic stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The oxide semiconductor layer is divided into multiple layers: a first oxide semiconductor layer (channel layer) and a second oxide semiconductor layer (protective layer). This segmentation allows the channel layer to be optimized for electrical performance while the protective layer shields it from process damage, resolving the contradiction between speed and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The protective oxide semiconductor layer is formed over the channel layer before subsequent production processes. This preliminary protective action prevents damage to the channel-forming region during manufacturing, thereby maintaining stable characteristics while enabling the use of top gate structure for high speed operation.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If the oxide semiconductor layer is directly exposed to form contact regions, then the manufacturing process is simplified, but the channel-forming region suffers damage and off-leakage current increases

Engineering Contradiction:
Improveprocess simplicityVSAvoidoff-leakage current control
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The oxide semiconductor layer is segmented into a channel layer and a protective layer. The protective layer is selectively removed in contact regions to expose the channel layer for electrode connection, while preserving the channel layer in non-contact regions. This resolves the contradiction by enabling simple manufacturing through selective removal while protecting the channel-forming region from damage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The protective oxide semiconductor layer is selectively removed only in regions where electrode contact is required, while being maintained in regions where channel protection is needed. This local differentiation allows both ease of manufacture (through selective exposure) and reliability (through protected channel regions).

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10593809B2Semiconductor device including oxide semiconductor thin-film transistor having multilayer structure oxide semiconductor layer
Publication Date: 2020.03.17 SHARP KK
  • US10593809B2 patent drawing
  • US10593809B2 patent drawing
  • US10593809B2 patent drawing

AI summary

A semiconductor device includes a substrate and an oxide semiconductor TFT including an oxide semiconductor layer supported by the substrate and having a multilayer structure including a protective oxide semiconductor layer and a channel oxide semiconductor layer disposed closer to the substrate than the protective oxide semiconductor layer, an upper insulating layer on the oxide semiconductor layer, an upper gate electrode disposed on the upper insulating layer, an interlayer insulating layer covering the oxide semiconductor layer and the upper gate electrode, and first and second electrodes electrically connected to the oxide semiconductor layer, wherein a first opening extends through at least the interlayer insulating layer and the protective oxide semiconductor layer, and exposes a portion of the channel oxide semiconductor layer, and the first electrode is disposed on the interlayer insulating layer and within the first opening, and is in direct contact with, within the first opening, the portion.