Oxide Semiconductor Transistor N-Type Buffer Layer Parasitic Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Transistors used in driver circuits for display devices require high on-state current and high-speed operation to reduce writing time of display images, but existing oxide semiconductor transistors face limitations in parasitic resistance and mobility.
Innovation Solution
A buffer layer with n-type conductivity is introduced between the oxide semiconductor layer and the source/drain electrode layers, reducing parasitic resistance and enhancing on-state current and mobility by using metal oxides like indium tin oxide or indium zinc oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buffer layer with n-type conductivity is introduced between the oxide semiconductor layer and source/drain electrode layers, then parasitic resistance is reduced and on-state current is improved, but device structure becomes more complex
Solution Approach 1:
An n-type conductivity buffer layer is introduced as an intermediary between the oxide semiconductor layer and the source/drain electrode layers. This buffer layer serves as a mediator that reduces parasitic resistance at the contact interfaces, thereby improving on-state current characteristics without requiring fundamental changes to the transistor architecture.
Solution Approach 2:
The buffer layer changes the electrical parameters at the contact interfaces by providing n-type conductivity, which reduces the contact resistance between the metal electrodes and the semiconductor channel. This parameter change directly addresses the parasitic resistance issue while maintaining structural simplicity.
2Speed
If high-speed operation is required for driver circuit transistors, then writing time is reduced, but parasitic resistance limits mobility and on-state current
Solution Approach 1:
The n-type buffer layer acts as an intermediary that facilitates faster carrier transport between the source/drain electrodes and the channel region. By reducing the contact resistance at these interfaces, the buffer layer enables higher on-state current and faster operation speeds, directly addressing the speed limitation imposed by parasitic resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a buffer layer significantly reduces parasitic resistance and improves on-state current and field-effect mobility, enabling high-speed operation and improved reliability of transistors in driver circuits.
Implementation Method 1
A buffer layer having n-type conductivity is formed between an oxide semiconductor layer which is a channel formation region of a transistor and a metal layer which is a source electrode layer or a drain electrode layer; thus, parasitic resistance is reduced
Data Source
AI summary
A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.