Oxide Semiconductor 3D-NAND Memory Erase Operation
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Solution Overview
Problem
Existing methods for performing an erase operation in 3D-NAND flash memories are ineffective when using an oxide semiconductor for the body portion, as they rely on hole injection techniques that are not applicable due to the wide bandgap and high energy barriers associated with oxide semiconductors.
Innovation Solution
A semiconductor device structure incorporating an oxide semiconductor with a specific configuration of conductors, insulators, and a functional layer, where the insulators are concentrically arranged around the conductors, and a driving method involving controlled potential applications to facilitate efficient erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductor is used for body portion to reduce power consumption and improve reliability, then device reliability is improved, but erase operation becomes impossible due to wide bandgap preventing hole injection
Solution Approach 1:
A P-type well is introduced as an intermediary structure between the substrate and the oxide semiconductor memory strings. This P-type well serves as a hole reservoir that can supply holes to the oxide semiconductor body portions during erase operations, overcoming the wide bandgap barrier while maintaining the reliability benefits of oxide semiconductor usage.
2Ease of operation
If conventional hole injection methods are used for erase operation, then erase function is achieved, but they cannot be applied to oxide semiconductor due to high energy barrier
Solution Approach 1:
The energy band structure is modified by introducing a P-type well with appropriate doping concentration and depth. This creates a favorable energy gradient that reduces the effective barrier for hole injection into the oxide semiconductor, enabling erase operations while maintaining device reliability through controlled parameter optimization.
3Ease of manufacture
If simple replacement from polysilicon to oxide semiconductor is made, then manufacturing simplicity is maintained, but erase operation is disabled due to material properties
Solution Approach 1:
The memory device structure is segmented into distinct functional regions: a P-type well region for hole supply and oxide semiconductor regions for memory storage. This segmentation allows each region to be optimized for its specific function while maintaining overall manufacturing simplicity through a unified fabrication process that forms both regions sequentially.
Data Source
AI summary
A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.