Oxide Semiconductor TFT Passivation for Composition Stability
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Solution Overview
Problem
The manufacturing process of thin film transistors (TFTs) using oxide semiconductor layers is prone to variance in characteristics due to exposure of peripheral edge and upper surface portions to etching liquids, leading to inconsistent film quality and electrical conduction issues.
Innovation Solution
A semiconductor device with a stacked oxide semiconductor layer structure where the proportion of pure metal is higher at the interface and upper surface portions compared to the bulk, and a passivation film or insulating film is formed as the upper layer to stabilize the composition ratio and reduce variance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wet etching is performed to form a pattern of the semiconductor layer, then the pattern is formed, but the peripheral edge portion and upper surface portion are exposed to etching liquid causing film quality change and composition ratio variation
Solution Approach 1:
The patent applies local quality by creating a multi-layer oxide semiconductor structure where different layers have different resistance characteristics. Specifically, a first oxide semiconductor layer with lower resistance and a second oxide semiconductor layer with higher resistance are stacked, allowing the upper layer to protect the lower channel-forming layer from etching liquid exposure while maintaining local electrical properties suitable for transistor operation.
Solution Approach 2:
The semiconductor layer is segmented into multiple oxide semiconductor layers with distinct functions. The first layer (lower resistance) serves as the primary conduction channel, while the second layer (higher resistance) acts as a protective overlay that reduces etching liquid penetration to the critical lower layer, thereby segmenting the protective and conduction functions across different layers.
2Reliability
If a second layer with higher resistance is provided on the protection layer side, then the influence on electrical conduction characteristics is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent utilizes parameter changes by controlling the resistance values of different oxide semiconductor layers. The first layer is designed with lower resistance (e.g., 10^-3 to 10^-6 ohm·cm) for efficient conduction, while the second layer has higher resistance (e.g., 10^-1 to 10^2 ohm·cm) for protection. This parameter differentiation allows the structure to simultaneously achieve good electrical conduction and etching resistance without requiring completely separate functional components.
Data Source
AI summary
In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).