Oxide Semiconductor Reconfigurable Circuit for Power-Off Data Retention
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining the connection relation between logic circuit units or circuit configuration for a long time after power supply voltage is stopped, and achieving high-speed operation with low power consumption, especially when using volatile SRAM or DRAM, and non-volatile flash memory with high drive voltage.
Innovation Solution
A semiconductor device incorporating an oxide semiconductor in the storage circuit, which includes a transistor and a capacitor, allows for the storage of data that maintains the circuit configuration even after power is stopped, enabling high-speed operation and low power consumption by using a lower drive voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory (SRAM/DRAM) is used for storage circuit, then high-speed operation is achieved, but data is lost when power supply voltage is stopped
Solution Approach 1:
The patent segments the storage circuit into two distinct parts: a volatile storage element (SRAM/DRAM) for high-speed operation and a non-volatile storage element for data retention. This segmentation allows each component to perform its specialized function optimally without compromising the other.
Solution Approach 2:
The patent merges volatile and non-volatile storage elements within the same storage circuit block. The volatile element handles rapid data access while the non-volatile element preserves data during power-off periods, combining the advantages of both memory types into a unified structure.
2Reliability
If non-volatile memory (flash memory) is used for storage circuit, then data is maintained after power supply voltage is stopped, but high drive voltage is required resulting in high power consumption
Solution Approach 1:
The patent segments the storage circuit into two distinct parts: a volatile storage element (SRAM/DRAM) for high-speed operation and a non-volatile storage element for data retention. This segmentation allows each component to perform its specialized function optimally without compromising the other.
Solution Approach 2:
The patent applies local quality by using different storage technologies in different locations within the storage circuit. The non-volatile element is specifically positioned to handle data retention requirements, while the volatile element handles high-speed operations, allowing each region to have optimized characteristics for its specific function.
3Reliability
If non-volatile memory (flash memory) is used for storage circuit, then data is maintained after power supply voltage is stopped, but high drive voltage is required resulting in slow operation speed
Solution Approach 1:
The patent segments the storage circuit into two distinct parts: a volatile storage element (SRAM/DRAM) for high-speed operation and a non-volatile storage element for data retention. This segmentation allows each component to perform its specialized function optimally without compromising the other.
Solution Approach 2:
The patent merges volatile and non-volatile storage elements within the same storage circuit block. The volatile element handles rapid data access while the non-volatile element preserves data during power-off periods, combining the advantages of both memory types into a unified structure.
Data Source
AI summary
An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.