Oxide Semiconductor Memory Refresh Timing Detection Circuit
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Solution Overview
Problem
Conventional DRAMs require frequent refresh operations to maintain data, leading to high power consumption and transistor deterioration, especially as memory capacity increases and transistor sizes decrease.
Innovation Solution
A semiconductor memory device with a refresh timing detection circuit using an oxide semiconductor and a reference cell to monitor drain current changes, allowing for reduced refresh frequency and lower power consumption, while also minimizing transistor wear.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to maintain data in conventional DRAM, then data retention is ensured, but power consumption increases and transistor deterioration accelerates
Solution Approach 1:
The patent changes the operational parameters of the memory device by using oxide semiconductor transistors with extremely low off-state current characteristics, enabling data retention without frequent refresh operations. This parameter change in transistor material properties allows reducing refresh frequency from conventional tens of milliseconds to much longer intervals, thereby reducing power consumption while maintaining data integrity
Solution Approach 2:
The oxide semiconductor transistor inherently maintains its off-state current characteristics over time and temperature variations, allowing the memory cell to self-maintain data without external refresh interventions. The material's stable electrical properties enable the system to serve itself by naturally preserving charge states without requiring continuous active management through frequent refresh cycles
2Reliability
If frequent refresh operations are performed to maintain data in conventional DRAM, then data retention is ensured, but transistor deterioration accelerates
Solution Approach 1:
The patent changes the transistor material to oxide semiconductor, which fundamentally alters the off-state current parameter to extremely low levels. This parameter change reduces the frequency of refresh operations required, thereby reducing the number of on-off cycles the transistor undergoes and extending its operational lifespan while maintaining data retention capability
Solution Approach 2:
The oxide semiconductor transistor's inherent stable electrical characteristics enable the memory cell to maintain data without frequent external refresh operations. This self-maintaining property reduces transistor switching activity, minimizing wear and extending the stationary object's (transistor) duration of action
3Measurement precision
If counter-based timing detection is used for refresh operations, then refresh timing is accurately controlled, but device complexity increases
Solution Approach 1:
The oxide semiconductor memory cell inherently maintains data without requiring external counter-based timing control for refresh operations. The cell's stable charge retention properties enable it to self-determine when refresh is needed, eliminating the need for complex counter circuits and timing control logic while maintaining accurate refresh timing based on actual data retention needs
Solution Approach 2:
The patent extracts and removes the counter-based timing detection circuit from the memory system. By relying on the oxide semiconductor's inherent stable characteristics, the design eliminates the disturbing complex timing control circuitry while maintaining sufficient refresh timing accuracy through the material's natural properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the frequency of refresh operations, decreases power consumption, and extends data retention time without the need for a counter-based timing detection system, resulting in a more efficient and durable memory device.
Implementation Method 1
a first transistor including an oxide semiconductor; and a first capacitor. When a potential is supplied to the first capacitor through the first transistor
Implementation Method 2
a refresh timing detection circuit including a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor, and a comparison circuit including a resistor and a comparator. When the drain current value of the third transistor is higher than a predetermined value, refresh operations of the memory cell array and the reference cell are performed
Data Source
AI summary
In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.