Oxide Semiconductor Transistor Self-Aligned Gate Structure
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Solution Overview
Problem
The miniaturization of transistors is hindered by challenges in patterning accuracy, particularly alignment accuracy, which affects the shape and characteristics of semiconductor devices, leading to decreased yield and on-state current.
Innovation Solution
A semiconductor device structure is developed with an oxide semiconductor film on an insulating substrate, featuring a source and drain electrode layer with a thickness greater than the oxide semiconductor film, a gate insulating film between 1 nm and 20 nm, and a gate electrode layer embedded within the source and drain electrode layers, allowing for self-aligned formation and reduced Loff region, thereby improving alignment accuracy and maintaining favorable transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the transistor is miniaturized to achieve high-speed operation and low power consumption, then the transistor size is reduced, but the alignment accuracy deteriorates
Solution Approach 1:
The source and drain electrode layers are formed with a thickness greater than the oxide semiconductor film thickness beforehand, creating protruding portions that extend beyond the oxide semiconductor film surface. This preliminary structural preparation enables subsequent self-aligned formation of the gate electrode layer, ensuring precise alignment even in miniaturized transistors without requiring high-precision alignment processes.
Solution Approach 2:
The gate electrode layer is formed in a self-aligned manner using the protruding portions of the source and drain electrode layers as alignment references. The structure automatically guides the gate electrode formation position, eliminating the need for external alignment processes and ensuring consistent alignment accuracy regardless of transistor size.
2Reliability
If the Loff region is reduced to maintain on-state current, then the channel region is optimized, but the alignment precision requirements increase
Solution Approach 1:
The self-aligned formation process using protruding portions as references automatically determines the gate electrode position, ensuring that the Loff region is minimized without requiring additional alignment precision. The structure itself provides the alignment reference, making the process robust against variations in transistor dimensions.
3Reliability
If the gate insulating film thickness is reduced to minimize Loff region, then the on-state current is maintained, but the manufacturing complexity increases
Solution Approach 1:
The gate insulating film thickness is controlled within a specific range (1 nm to 20 nm) to optimize the balance between minimizing the Loff region and maintaining manufacturability. This parameter optimization ensures that the on-state current is preserved while avoiding excessively thin films that would complicate the manufacturing process.
Data Source
AI summary
A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield. The semiconductor device has a structure including an oxide semiconductor film provided over a substrate having an insulating surface; a source electrode layer and a drain electrode layer which are provided in contact with side surfaces of the oxide semiconductor film and have a thickness larger than that of the oxide semiconductor film; a gate insulating film provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and a gate electrode layer provided in a depressed portion formed by a step between a top surface of the oxide semiconductor film and top surfaces of the source electrode layer and the drain electrode layer.