Self-Aligned Oxide Semiconductor Transistor Yield
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Solution Overview
Problem
As transistors are miniaturized to achieve high-speed operation, low power consumption, and high integration, the yield of the manufacturing process decreases, and there is a need for improved on-state characteristics, particularly in achieving high-speed response and operation while maintaining high yield.
Innovation Solution
A semiconductor device structure is developed with a conductive film and interlayer insulating layer stacked over an oxide semiconductor layer, where the gate insulating layer, gate electrode layer, and insulating layers are formed, and the source and drain electrode layers are created in a self-aligned manner without using a resist mask for etching, allowing for precise processing and reduced contact resistance through low-resistance regions in the oxide semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the transistor is miniaturized to achieve high-speed operation and high integration, then the operating speed and integration density are improved, but the manufacturing yield decreases due to increased process variability
Solution Approach 1:
The source and drain electrode layers are formed in a self-aligned manner before the gate insulating layer is deposited, establishing precise positional relationships in advance. This preliminary alignment eliminates the need for subsequent resist mask etching steps that would introduce variability in miniaturized transistors, thereby maintaining high manufacturing yield while achieving the required miniaturization for high-speed operation
Solution Approach 2:
The conductive film automatically forms the source and drain electrode layers in their correct positions through the self-aligned process, where the film deposition and subsequent removal of the gate insulating layer naturally define the electrode boundaries. This self-service mechanism eliminates human intervention in the alignment process, ensuring consistent precision across all miniaturized transistors and maintaining high yield
2Productivity
If the transistor is miniaturized to achieve high integration, then the integration density is improved, but the on-state characteristics deteriorate due to reduced source and drain region thickness
Solution Approach 1:
The source and drain electrode layers are extended in the vertical dimension by forming them before the gate insulating layer deposition, allowing the electrodes to penetrate through multiple layers. This dimensional extension compensates for the reduced horizontal thickness caused by miniaturization, maintaining sufficient conductive path length and carrier injection capability for excellent on-state characteristics while achieving high integration density
Solution Approach 2:
The source and drain electrode layers are nested within the stack of the oxide semiconductor layer, gate insulating layer, and conductive film. This nested structure allows the electrodes to be embedded in multiple layers, effectively increasing their functional thickness and ensuring adequate electrical performance even when the overall transistor dimensions are reduced for high integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of miniaturized transistors with high yield and excellent on-state characteristics by reducing contact resistance and allowing for thicker source and drain regions, leading to improved performance and reliability.
Implementation Method 1
the conductive film is divided by removing the gate insulating layer
Implementation Method 2
The oxide semiconductor layer includes low-resistance regions whose resistance is lowered by introduction of an impurity element
Data Source
AI summary
A miniaturized transistor is provided with high yield. Further, a semiconductor device which has high on-state characteristics and which is capable of high-speed response and high-speed operation is provided. In the semiconductor device, an oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an insulating layer, a conductive film, and an interlayer insulating layer are stacked in this order. A source electrode layer and a drain electrode layer are formed in a self-aligned manner by cutting the conductive film so that the conductive film over the gate electrode layer and the conductive layer is removed and the conductive film is divided. An electrode layer which is in contact with the oxide semiconductor layer and overlaps with a region in contact with the source electrode layer and the drain electrode layer is provided.