Oxide Semiconductor Transistor With Side-Contact Electrodes

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Solution Overview

Problem

Miniaturization of transistors is hindered by the short-channel effect, which leads to degradation in electrical characteristics such as threshold voltage, subthreshold swing, and increased leakage current, particularly in oxide semiconductor devices due to low carrier density.

Innovation Solution

A semiconductor device structure is developed with an oxide semiconductor layer, source and drain electrodes, and a gate electrode, where the oxide semiconductor layer is in contact with the electrodes only at its side surfaces, and an insulating layer covers the upper surface, creating a high resistance region near the interface to relax the electric field and reduce the short-channel effect.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the transistor channel length is reduced to achieve miniaturization, then the device size and power consumption are improved, but the short-channel effect causes degradation in electrical characteristics such as threshold voltage, subthreshold swing, and increased leakage current

Engineering Contradiction:
Improvechannel lengthVSAvoidelectrical characteristics
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by forming a high resistance region specifically at the interface between the oxide semiconductor layer and source/drain electrodes, while maintaining different resistance characteristics in other regions. This localized modification of electrical properties allows the channel length to be reduced without causing short-channel effects, as the high resistance region suppresses carrier generation at the critical interface area where the short-channel effect would otherwise occur

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements preliminary anti-action by proactively creating a high resistance region before the short-channel effect can manifest. This high resistance region is formed in advance at the source/drain electrode interfaces to prevent excessive carrier generation that would lead to threshold voltage degradation and increased leakage current. By establishing this protective high resistance region beforehand, the patent counteracts the harmful effects of channel length reduction before they occur

Inventive Principle:
Principle #9Preliminary anti-action

2Productivity

If the transistor is miniaturized to increase manufacturing efficiency, then the production capacity is improved, but defects from manufacturing processes become more significant

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoiddefect control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by modifying the resistance parameter at the source/drain electrode interfaces through controlled formation of a high resistance region. This parameter modification (increasing resistance at specific locations) makes the device more tolerant to manufacturing variations and defects, allowing miniaturization to proceed without proportionally increasing defect impact. The high resistance region acts as a buffer that stabilizes electrical characteristics even when manufacturing precision varies

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9391209B2Semiconductor device
Publication Date: 2016.07.12 SEMICON ENERGY LAB CO LTD
  • US9391209B2 patent drawing
  • US9391209B2 patent drawing
  • US9391209B2 patent drawing

AI summary

An object is to provide a semiconductor device including an oxide semiconductor in which miniaturization is achieved while favorable characteristics are maintained. The semiconductor includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, and an insulating layer provided in contact with the oxide semiconductor layer. A side surface of the oxide semiconductor layer is in contact with the source electrode or the drain electrode. An upper surface of the oxide semiconductor layer overlaps with the source electrode or the drain electrode with the insulating layer interposed between the oxide semiconductor layer and the source electrode or the drain electrode.