Oxide Semiconductor Sidewalls for Short Channel Reliability
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Solution Overview
Problem
Miniaturization of semiconductor elements with oxide semiconductors is hindered by the difficulty in reducing the space between source and drain electrode layers, limiting channel length and increasing power consumption, while maintaining reliability and preventing short circuits.
Innovation Solution
The provision of sidewalls on source and drain electrode layers in top-gate semiconductor elements with oxide semiconductors, which allows for a short channel length, improved gate insulating layer coverage, and reduced parasitic capacitance, using a method that includes forming a conductive layer, insulating layers, and etching to create tapered shapes, thereby enhancing manufacturing ease and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the space between source electrode layer and drain electrode layer is reduced to miniaturize the semiconductor element, then the channel length decreases and operation speed increases, but the gate insulating layer coverage becomes insufficient and short circuits occur
Solution Approach 1:
The invention introduces a vertical dimension by forming sidewalls on the source and drain electrode layers. This three-dimensional structure allows the gate insulating layer to extend vertically along the sidewalls, providing sufficient coverage even when the horizontal space between source and drain is reduced. The sidewalls create an offset region that prevents direct contact between the gate electrode and source/drain electrodes, eliminating short circuits while maintaining short channel length for high-speed operation.
Solution Approach 2:
The sidewalls act as an intermediary structure between the source/drain electrode layers and the gate insulating layer. These sidewalls provide a physical barrier and extension surface that enables the gate insulating layer to achieve adequate coverage without requiring increased horizontal spacing. The intermediary sidewall structure resolves the conflict between miniaturization and reliability by mediating the spatial relationship between competing components.
2Length of moving object
If photo process is used to reduce the space between source electrode layer and drain electrode layer, then miniaturization is attempted, but the manufacturing precision is limited and minute semiconductor elements cannot be manufactured
Solution Approach 1:
The invention replaces the photo process (optical method) with a physical structuring method using sidewalls. Instead of relying on photolithography resolution limits to define the space between source and drain electrodes, the patent uses mechanical/physical formation of sidewall structures through deposition and etching processes. This substitution enables precise control of the offset region dimensions through film thickness control rather than optical diffraction limits, achieving superior manufacturing precision for minute semiconductor elements.
3Speed
If the channel length is reduced to increase operation speed, then power consumption decreases, but the gate insulating layer coverage becomes insufficient and reliability deteriorates
Solution Approach 1:
By forming sidewalls on the source and drain electrode layers, the invention extends the gate insulating layer coverage into the vertical dimension. This allows the gate insulating layer to maintain adequate thickness and coverage along the sidewall surfaces even when the horizontal channel length is reduced. The vertical extension provided by sidewalls decouples the relationship between channel length and gate coverage, enabling short-channel high-speed devices with reliable insulation.
Data Source
AI summary
The semiconductor element includes an oxide semiconductor layer on an insulating surface; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer. The source electrode layer and the drain electrode layer have sidewalls which are in contact with a top surface of the oxide semiconductor layer.