Signal Processing Circuit With Oxide Semiconductor Nonvolatile Memory
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Solution Overview
Problem
Existing signal processing circuits face issues with data loss when power is stopped due to the use of volatile memory circuits, and nonvolatile memory circuits suffer from fatigue and low access speed, making them unsuitable for applications requiring short power-off periods.
Innovation Solution
A signal processing circuit is designed with a combination of volatile and nonvolatile memory circuits, where data is stored in nonvolatile memory during power-off, using transistors with extremely low off-state current and capacitors to maintain data integrity, allowing for high-speed data access and reduced power consumption through a normally-off driving method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ferroelectric memory element is used for nonvolatile storage, then data can be retained during power-off, but the memory element fatigues due to repeated data writing, limiting the number of rewriting times
Solution Approach 1:
A capacitor is introduced as an intermediary component between the transistor and the data storage node. The capacitor stores electrical charge that maintains the logic state without requiring repeated writing operations to the ferroelectric material, thereby protecting the ferroelectric element from fatigue while enabling nonvolatile data retention.
2Reliability
If a flash memory is used for nonvolatile storage, then data can be retained during power-off, but memory elements deteriorate due to repeated high voltage application for data rewriting
Solution Approach 1:
The capacitor serves as a mediator that allows data to be read from and written to the nonvolatile memory without requiring repeated high voltage pulses. The capacitor maintains the stored state through electrical charge retention, enabling low-voltage operation and reducing stress on the memory elements during repeated access operations.
3Reliability
If data is stored in external memory device during power-off, then data loss is prevented, but it takes a long time to return data from external memory, making it unsuitable for short power-off periods
Solution Approach 1:
The memory system is segmented into two functional parts: a volatile memory circuit for high-speed data processing during operation, and a nonvolatile memory circuit with capacitor-based storage for data retention during power-off. This segmentation allows each component to optimize its function without compromising the other, enabling both fast access during operation and reliable retention during power-off periods.
Solution Approach 2:
The invention changes the fundamental storage parameter from charge-based volatile memory to capacitor-based nonvolatile memory. The capacitor's ability to retain charge without power enables data persistence during power-off periods while maintaining compatibility with standard logic voltage levels, thus avoiding the time penalty of external memory devices.
4Speed
If volatile memory circuits are used for register and cache memory, then high-speed data access is achieved, but data is lost when power supply is stopped
Solution Approach 1:
The invention merges volatile and nonvolatile memory technologies into a unified system. The volatile memory circuit provides high-speed access during operation, while the nonvolatile memory circuit with capacitor-based storage provides data retention during power-off. The two memory types work together through shared access paths and control logic, achieving both high speed and reliability in a single integrated solution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively maintains data integrity during power-off periods, reduces power consumption, and enhances operation speed by using transistors with low off-state current and capacitors for data storage, improving durability and reliability.
Implementation Method 1
a capacitor in which one of a pair of electrodes (hereinafter referred to as one electrode) is electrically connected to a node which is set in a floating state when the transistor is turned off
Implementation Method 2
a transistor with extremely low off-state current
Data Source
AI summary
To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.