Oxide Semiconductor Device With Tapered Insulating Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with channels made of amorphous silicon have low mobility and high off-current, while those with channels made of low-temperature polysilicon or single crystalline silicon have complex structures and high off-current, limiting their use in display devices due to substrate size and processing temperature constraints.
Innovation Solution
A semiconductor device with a channel formed of an oxide semiconductor, featuring a tapered insulating layer and a specific electrode configuration that allows for a shorter channel length and reduced in-plane variance, enabling higher on-current and improved performance in display devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a channel is formed of amorphous silicon to simplify structure and enable low-temperature processing, then manufacturing complexity is reduced and substrate size can be increased, but mobility decreases and off-current increases
Solution Approach 1:
The patent changes the material parameter from conventional silicon (amorphous, low-temperature polysilicon, or single crystalline) to oxide semiconductor, which enables both simple structure formation at low temperatures and simultaneously achieves low off-current characteristics, resolving the contradiction between ease of manufacture and reliability
Solution Approach 2:
The patent uses a composite structure combining oxide semiconductor channel layer with specific insulating layers (first insulating layer with side wall, gate insulating layer) and electrode configurations, creating a composite device structure that achieves both manufacturing simplicity and low off-current
2Reliability
If a channel is formed of low-temperature polysilicon or single crystalline silicon to increase mobility, then on-current improves, but structure complexity increases and manufacturing process becomes complicated
Solution Approach 1:
The patent changes the channel material from low-temperature polysilicon or single crystalline silicon to oxide semiconductor, which can be formed with simpler amorphous structure deposition processes while achieving comparable or sufficient mobility for display device applications, thereby reducing manufacturing complexity
Solution Approach 2:
The patent adopts oxide semiconductor that can be formed by simpler, less expensive amorphous deposition techniques rather than complex polysilicon or single crystalline growth processes, achieving cost-effective manufacturing with adequate performance for the intended application
3Reliability
If channel length is shortened to increase on-current in oxide semiconductor devices, then mobility limitation is compensated, but photolithography precision requirements increase due to minimum mask pattern size constraints
Solution Approach 1:
The patent introduces a vertical dimension by forming the oxide semiconductor layer on the side wall of the first insulating layer, creating a three-dimensional structure where the channel extends vertically along the side wall. This dimensional change allows channel length control through layer thickness rather than horizontal photolithography, bypassing the 2 μm mask pattern limitation
Solution Approach 2:
The patent segments the channel formation into distinct functional regions: the first insulating layer with side wall provides structural definition, the oxide semiconductor layer forms the active channel on the side wall, and the gate electrode provides control. This segmentation allows independent optimization of each component, with channel length determined by the first insulating layer thickness rather than photolithography
Data Source
AI summary
A semiconductor device includes a first insulating layer having a first side wall, an oxide semiconductor layer located on the first side wall, a gate insulating layer located on the oxide semiconductor layer, the oxide semiconductor layer being located between the first side wall and the gate insulating layer, a gate electrode facing the oxide semiconductor layer located on the first side wall, the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a first electrode located below the oxide semiconductor layer and connected with one portion of the oxide semiconductor layer, and a second electrode located above the oxide semiconductor layer and connected with the other portion of the oxide semiconductor layer.