Oxide Semiconductor TFT Barrier Layers for Threshold Voltage Stability
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Solution Overview
Problem
Oxide semiconductor-based thin-film transistors (TFTs) face degradation due to light exposure and fabrication processes, leading to shifts in threshold voltage, which affects their reliability and consistency.
Innovation Solution
Incorporating intermediate and first barrier layers with specific materials (e.g., TiOx, TaOx, SrTiO3, BaZrO3, ZrO2, HfO2, Al2O3, MgO, Cu2O, CuAlO2, SiO2, SrCu2O2, and Al2O3) between the oxide semiconductor layers and gate insulating layers to prevent carrier trapping and reduce threshold voltage shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If intermediate barrier layers are added to prevent carrier trapping, then threshold voltage stability is improved, but device structure complexity increases
Solution Approach 1:
The patent segments the gate stack structure into distinct functional layers: oxide semiconductor layers, gate insulating layers, and intermediate barrier layers. By dividing the structure into specialized segments, each layer can be optimized for its specific function (carrier transport, electrical isolation, or carrier blocking). This segmentation approach improves threshold voltage stability through the intermediate barrier layers while keeping the complexity manageable by clearly defining the role and position of each layer in the stack.
Data Source
Figure 1a~1c
Figure 1d~1g
Figure 1h~2b
AI summary
A thin-film transistor includes a substrate, a first gate electrode formed on the substrate, a first active layer that is formed on the substrate and includes a first oxide semiconductor layer and a first barrier layer, a second active layer that is formed on the first active layer and includes a second oxide semiconductor layer and an intermediate barrier layer, a gate insulating layer that is formed on the second active layer, a second gate electrode that is formed on the gate insulating layer and is electrically connected to the first gate electrode, an interlayer insulating film formed on the second gate electrode, the first active layer and the second active layer, and a source electrode and a drain electrode electrically connected to the first active layer and the second active layer.