Oxide Semiconductor TFT Cu Diffusion Barrier

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The diffusion of Cu or Cu alloys into the oxide semiconductor layer in TFTs during the manufacturing process leads to unstable device characteristics, particularly in inversely staggered (bottom gate top contact type) configurations, affecting the channel region and overall performance.

Innovation Solution

A semiconductor device with a two-layer oxide semiconductor structure, where the upper layer acts as a buffer and the lower layer as the channel, and source/drain electrodes are designed with a Cu-containing major layer and a Ti or Mo-containing lower layer, with the lower layer electrode positioned ahead of the major layer electrode to prevent Cu diffusion, along with a channel etch type configuration to reduce etching damage and film defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Cu or Cu alloy is used for source/drain electrodes to reduce electrical resistance, then electrical resistance is reduced, but Cu diffuses into the oxide semiconductor layer causing unstable device characteristics

Engineering Contradiction:
Improvedevice characteristics stabilityVSAvoidCu diffusion into oxide semiconductor layer
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A barrier layer made of Ti, Mo, or W is introduced between the Cu-containing source/drain electrodes and the oxide semiconductor layer. This intermediary layer prevents Cu diffusion into the semiconductor while maintaining electrical connectivity, thus resolving the contradiction between low resistance and preventing harmful diffusion.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The source/drain electrode structure is segmented into multiple layers: a Cu-containing major layer for low resistance and a Ti/Mo/W-containing lower layer in contact with the oxide semiconductor layer to prevent diffusion. This segmentation allows each layer to fulfill its specific function independently.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If oxide semiconductor TFT is used to reduce manufacturing steps and cost, then manufacturing complexity is reduced, but metal element diffusion from source/drain layer into oxide semiconductor layer causes threshold voltage variation

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidthreshold voltage control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The barrier layer acts as an intermediary that prevents metal element diffusion during the manufacturing process, ensuring stable threshold voltage characteristics while maintaining the simplicity of the oxide semiconductor TFT manufacturing process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The barrier layer is formed in advance before the oxide semiconductor layer is deposited, establishing a diffusion barrier prior to potential contamination. This preliminary action ensures that subsequent manufacturing steps do not compromise threshold voltage stability.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If Cu-containing source/drain electrodes are used to achieve low resistance, then electrical conductivity is improved, but diffusion of Cu into channel region contaminates the channel and destabilizes device characteristics

Engineering Contradiction:
Improvedevice characteristics stabilityVSAvoidchannel contamination from Cu diffusion
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The Ti/Mo/W lower layer serves as an intermediary barrier that blocks Cu diffusion into the channel region while allowing electrical current to pass through, thus preventing channel contamination without sacrificing conductivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The electrode structure exhibits local quality differentiation: the major layer contains Cu for low resistance where it contacts the oxide semiconductor, while the lower layer contains Ti/Mo/W for diffusion prevention where it contacts the channel region. Each region has optimized material composition for its specific function.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively suppresses Cu diffusion into the oxide semiconductor layer, stabilizing TFT characteristics and reducing manufacturing costs while maintaining low resistance for the electrodes.

Implementation Method 1

the source/drain electrodes include a lower layer electrode which is in contact with the oxide semiconductor layer and which does not contain Cu, and a major layer electrode which is provided over the lower layer electrode and which contains Cu

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS10164118B2Semiconductor device and method for producing same
Publication Date: 2018.12.25 SHARP KK
  • US10164118B2 patent drawing
  • US10164118B2 patent drawing
  • US10164118B2 patent drawing

AI summary

A semiconductor device (100A) includes a substrate (101) and a thin film transistor (10) supported by the substrate. The thin film transistor includes a gate electrode (102), an oxide semiconductor layer (104), a gate insulating layer (103), a source electrode (105) and a drain electrode (106). The oxide semiconductor layer includes an upper semiconductor layer (104b) which is in contact with the source electrode and the drain electrode and which has a first energy gap, and a lower semiconductor layer (104a) which is provided under the upper semiconductor layer and which has a second energy gap that is smaller than the first energy gap. The source electrode and the drain electrode include a lower layer electrode (105a, 106a) which is in contact with the oxide semiconductor layer and which does not contain Cu, and a major layer electrode (105b, 106b) which is provided over the lower layer electrode and which contains Cu. An edge of the lower layer electrode is at a position ahead of an edge of the major layer electrode.