Oxide Semiconductor TFT Double Gate Structure for Active Matrix Substrates
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Solution Overview
Problem
Oxide semiconductor TFTs with a double gate structure face reliability issues due to over-etching of the gate insulating layer, which can lower the performance and reliability of active matrix substrates used in display devices.
Innovation Solution
An active matrix substrate design that includes an oxide semiconductor TFT with a specific structure featuring a lower insulating layer, an oxide semiconductor layer, an upper insulating layer, and a gate electrode configuration that prevents over-etching, along with an extension region that connects adjacent pixel regions, enhancing the reliability and performance of the TFTs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If oxide semiconductor TFTs with double gate structure are used to increase ON current, then the ON current increases, but the gate insulating layer may be over-etched during patterning, lowering reliability
Solution Approach 1:
The gate structure is segmented into a lower gate electrode and an upper gate electrode separated by the oxide semiconductor layer. This segmentation allows independent optimization of each gate's function: the lower gate provides strong field effect for high ON current, while the upper gate can be patterned separately to avoid over-etching the gate insulating layer during manufacturing
Solution Approach 2:
The lower gate electrode is formed first before the oxide semiconductor layer and upper gate electrode. This preliminary formation allows the lower gate to establish strong electrical field control early in the process, enabling high ON current. Subsequently, the upper gate is formed with proper insulation, preventing over-etching issues during final patterning
2Ease of manufacture
If oxide semiconductor TFTs are used instead of polycrystalline silicon, then the manufacturing process becomes simpler and can be applied to large area devices, but the mobility is still lower than polycrystalline silicon
Solution Approach 1:
The invention uses a composite gate structure with both lower and upper gate electrodes, combining the advantages of simple oxide semiconductor fabrication with enhanced electrical characteristics. The dual-gate configuration provides superior field effect and carrier control compared to single-gate structures, achieving high mobility equivalent to polycrystalline silicon while maintaining the manufacturing simplicity of oxide semiconductors
3Device complexity
If the upper insulating layer is patterned to form the upper gate electrode, then the gate electrode structure is completed, but the lower insulating layer surface may be over-etched, lowering TFT reliability
Solution Approach 1:
The oxide semiconductor layer serves as an intermediary protective layer between the upper insulating layer patterning process and the lower insulating layer. During upper gate electrode formation, the oxide semiconductor layer prevents etching damage from reaching the lower insulating layer, thus avoiding over-etching while allowing complete gate structure formation
Solution Approach 2:
The oxide semiconductor layer is deposited beforehand to provide a protective cushioning layer. This layer absorbs or prevents the harmful effects of over-etching during upper gate patterning, protecting the lower insulating layer from damage before the actual patterning operation occurs
Data Source
AI summary
Each of pixel regions of an active matrix substrate (1002) includes: a lower insulating layer (5); an oxide semiconductor layer (7) that is arranged on the lower insulating layer and includes an active region (7a) of an oxide semiconductor TFT; an upper insulating layer (9) that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer (10) that is arranged on the upper insulating layer and includes an upper gate electrode (10a) and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layer 7 further includes an extension region (7e) that extends from the active region (7a) in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region (7e) is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer (9) interposed therebetween, and includes a portion that extends so as to overlap with the one of the plurality of gate bus lines.