Oxide Semiconductor TFT Low-Resistance Regions via Hydrogen Diffusion
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Solution Overview
Problem
The existing method for manufacturing oxide semiconductor TFTs requires multiple manufacturing steps, including plasma treatment after gate insulating film etching, which increases complexity.
Innovation Solution
A method that forms low-resistance source and drain regions by diffusing hydrogen from the source and drain electrodes into the oxide semiconductor layer, reducing the number of manufacturing steps and simplifying the process, while maintaining favorable electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plasma treatment is performed after gate insulating film etching to form source/drain regions, then the oxide semiconductor TFT can be manufactured, but the number of manufacturing steps increases
Solution Approach 1:
The patent combines the source/drain region formation process with the gate electrode formation process by using the same etching steps. The gate electrode pattern formation and source/drain region formation are merged into a single etching operation, eliminating the need for separate plasma treatment steps while maintaining proper electrical characteristics.
Solution Approach 2:
The patent performs preliminary hydrogen plasma treatment on the oxide semiconductor layer before gate electrode formation. This preliminary action creates low-resistance regions that will become the source and drain regions, so that when etching occurs later, these regions are already prepared with appropriate electrical properties, eliminating the need for post-etching plasma treatment.
2Reliability
If multiple plasma treatment steps are used to form low-resistance source and drain regions, then electrical performance is improved, but manufacturing time increases
Solution Approach 1:
Multiple plasma treatment steps are merged into a single integrated process. The hydrogen plasma treatment for creating low-resistance regions is combined with the etching process for gate electrode formation, reducing the total number of processing steps while maintaining the electrical performance benefits of low-resistance source and drain regions.
Solution Approach 2:
The low-resistance region formation is performed as a preliminary action before gate electrode etching. By pre-forming these regions with hydrogen plasma treatment, the subsequent etching process can proceed without requiring additional plasma treatment steps, thereby reducing manufacturing time while preserving electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a TFT with fewer manufacturing steps and improved electrical performance, specifically by forming low-resistance regions that connect to the source and drain electrodes with controlled carrier concentrations, enhancing the device's operational efficiency.
Implementation Method 1
a method that forms low-resistance source and drain regions by diffusing hydrogen from the source and drain electrodes into the oxide semiconductor layer
Data Source
AI summary
A semiconductor device (100A) has an oxide semiconductor layer (11). The oxide semiconductor layer (11) has a channel region (11c), and a source region (11s) and drain region (11d) positioned on respective sides of the channel region (11c). The source region (11s) has a low-resistance source region (11sx) that has a lower resistance than the channel region (11c), and the drain region (11d) has a low-resistance drain region (11dx) that has a lower resistance than the channel region (11c). The carrier concentrations of the low-resistance source region (11sx) and the low-resistance drain region (11dx) become progressively lower from a connecting portion between a source electrode (17) and the low-resistance source region (11sx) and a connecting portion between a drain electrode (18) and the low-resistance drain region (11dx) towards the channel region (11c).