Oxide Semiconductor TFT Layered Structure for Threshold Voltage Stability
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Solution Overview
Problem
The reliability of oxide semiconductor TFTs with layered structures, which include two layers with different compositions, is compromised due to potential etching damage and diffusion of source metal layers, leading to fluctuations in threshold voltage and reduced performance.
Innovation Solution
A semiconductor device with a TFT structure featuring a gate electrode, gate insulating layer, and an oxide semiconductor layer with a layered structure comprising a first and second oxide semiconductor layer, where the first layer has a higher In atomic ratio than Zn, and the second layer has a lower In atomic ratio than Zn, and the oxide semiconductor layer has a forward tapered side surface, formed by annealing and etching processes to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an oxide semiconductor layer includes two layers having different compositions (upper layer and lower layer), then the mobility and threshold voltage can be adjusted, but the reliability may lower due to etching damage and source metal diffusion
Solution Approach 1:
The patent applies local quality by creating distinct composition zones within the oxide semiconductor layer. The lower layer (first oxide semiconductor layer) has a composition optimized for adhesion to the gate insulating layer and resistance to source metal diffusion, while the upper layer (second oxide semiconductor layer) has a composition optimized for high carrier mobility. This spatial differentiation of material properties allows each layer to perform its specific function optimally without compromising overall reliability.
Solution Approach 2:
The patent employs composite materials by combining two different oxide semiconductor compositions in a layered structure. The first oxide semiconductor layer contains a specific ratio of metal elements (e.g., In-Ga-Zn-O with particular atomic ratios) that provides structural stability and resistance to diffusion, while the second oxide semiconductor layer contains a different composition that provides high mobility. This composite structure leverages the complementary properties of different materials to achieve both reliability and high performance.
2Ease of manufacture
If the oxide semiconductor layer has a reverse tapered shape, then the manufacturing process is simpler, but the source metal layer may diffuse and threshold voltage fluctuates
Solution Approach 1:
The patent applies preliminary action by forming the gate insulating layer with specific properties (such as a nitrogen-containing layer or a layered structure) before depositing the oxide semiconductor layers. This preliminary preparation of the gate insulating layer creates a foundation that prevents source metal diffusion and supports the formation of the forward tapered oxide semiconductor layer, thereby preventing threshold voltage fluctuations before the actual semiconductor layer formation occurs.
Solution Approach 2:
The patent utilizes curvature by specifying that the oxide semiconductor layer should have a forward tapered shape rather than a reverse tapered or flat shape. This forward tapered geometry (where the layer is wider at the top than at the bottom) prevents source metal diffusion by creating a physical barrier and reduces the risk of threshold voltage fluctuations. The curved/tapered profile is achieved through controlled deposition conditions and layer composition design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the reliability of oxide semiconductor TFTs by reducing etching damage and source metal diffusion, maintaining high mobility and stability of the TFT characteristics, and preventing threshold voltage fluctuations.
Implementation Method 1
annealing the first oxide semiconductor film and the second oxide semiconductor film at a temperature of 400° C. or more and 480° C. or less
Implementation Method 2
etching the first oxide semiconductor film and the second oxide semiconductor film using an etchant with an etching mask interposed therebetween
Data Source
AI summary
A semiconductor device (100) includes a TFT (10) supported on a substrate (11), wherein the TFT (10) includes a gate electrode (12g), a gate insulating layer (14) that covers the gate electrode (12g), and an oxide semiconductor layer (16) that is formed on the gate insulating layer (14). The oxide semiconductor layer 16 has a layered structure including a first oxide semiconductor layer (16a) in contact with the gate insulating layer (14) and a second oxide semiconductor layer (16b) layered on the first oxide semiconductor layer (16a). The first oxide semiconductor layer (16a) and the second oxide semiconductor layer (16b) both include In, Ga and Zn; an In atomic ratio of the first oxide semiconductor layer (16a) is greater than a Zn atomic ratio thereof, and an In atomic ratio of the second oxide semiconductor layer (16b) is smaller than a Zn atomic ratio thereof; and the oxide semiconductor layer (16) has a side surface of a forward tapered shape.