Oxide Semiconductor Thin Film Transistor Substrate with Localized Carrier Concentration
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Solution Overview
Problem
Conventional thin film transistors exhibit low saturation mobility, which limits their performance in display devices using oxide semiconductor gates and organic light-emitting diodes, necessitating the development of a solution to enhance mobility without compromising the device's integrity.
Innovation Solution
A thin film transistor substrate is designed with a specific structure including a substrate, gate electrode, gate insulation layer, oxide semiconductor pattern, etch stopper, signal electrode, and passivation layer, where the oxide semiconductor pattern has distinct carrier concentration areas and a signal electrode made of titanium or titanium oxide, optimized to achieve high saturation mobility under high hydrogen conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional thin film transistor structure is used, then device simplicity is maintained, but saturation mobility remains low
Solution Approach 1:
The patent applies local quality by creating distinct regions within the oxide semiconductor layer with different carrier concentrations. The first area has carrier concentration of 10^17 to 10^19 cm^-3 while the second area has lower carrier concentration, optimizing different functional regions for specific performance characteristics and achieving high saturation mobility through localized property differentiation.
Solution Approach 2:
The patent employs composite materials by combining multiple layers with different properties: oxide semiconductor pattern, etch stopper layer, signal electrode layer (titanium or titanium oxide), and passivation layer. This multi-layer composite structure achieves high saturation mobility while maintaining device integrity and functionality.
2Reliability
If passivation layer is formed under high hydrogen condition to increase saturation mobility, then mobility improves, but carrier concentration control becomes challenging
Solution Approach 1:
The patent segments the oxide semiconductor layer into two distinct areas with different carrier concentrations. The first area (10^17 to 10^19 cm^-3) and second area (lower carrier concentration) are formed through selective processing, allowing precise control of electrical properties in different regions while achieving high saturation mobility under high hydrogen conditions.
Solution Approach 2:
The patent utilizes parameter changes by controlling carrier concentration in the oxide semiconductor layer through high hydrogen condition processing. By adjusting hydrogen exposure parameters and forming distinct carrier concentration regions, the patent achieves optimized saturation mobility while maintaining manufacturing precision through controlled parameter variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The substrate configuration significantly increases current levels and saturation mobility, making the thin film transistor switching-adjustable and suitable for high-performance display devices while maintaining semiconductive properties.
Implementation Method 1
an oxide semiconductor pattern disposed on the gate insulation layer... The oxide semiconductor pattern has a first area whose carrier concentration is in a range of about 10^17 per cubic centimeter (cm^−3) to about 10^19 per cubic centimeter (cm^−3), and a second area whose carrier concentration less than the carrier concentration of the first area
Implementation Method 2
a signal electrode which overlaps a portion of the etch stopper and the second area... The signal electrode may include titanium or titanium oxide
Data Source
AI summary
A thin film transistor substrate includes a substrate, a gate electrode disposed on the substrate, a gate insulation layer disposed on the gate electrode, an oxide semiconductor pattern disposed on the gate insulation layer, where the oxide semiconductor pattern includes a first area whose carrier concentration is in a range of about 1017 per cubic centimeter to about 1019 per cubic centimeter and a second area whose carrier concentration is less than the carrier concentration of the first area, an etch stopper disposed on the oxide semiconductor pattern, where the etch stopper covers the first area and the second area of the oxide semiconductor pattern, a signal electrode partially overlapping the etch stopper and the second area, and a passivation layer which covers the etch stopper and the signal electrode.


