Layered Oxide Semiconductor TFT with Offset Sub-Gate Electrode
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Solution Overview
Problem
Conventional oxide semiconductor TFTs with an offset structure face reliability issues due to auxiliary gate electrodes affecting TFT characteristics and parasitic capacitance, leading to suboptimal ON characteristics and reliability.
Innovation Solution
A semiconductor device with a layered oxide semiconductor TFT structure, including a main gate electrode and a sub-gate electrode in different layers, with an offset region that overlaps the sub-gate electrode, optimizing the insulating layers for reduced parasitic capacitance and enhanced ON characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an offset structure is used to reduce parasitic capacitance, then operation speed is improved, but ON current decreases
Solution Approach 1:
The gate electrode is divided into two separate electrodes: a main gate electrode and an offset gate electrode. The main gate electrode overlaps with the channel formation region to control channel formation, while the offset gate electrode is positioned in the offset region to reduce parasitic capacitance. This segmentation allows each electrode to independently optimize its function, resolving the contradiction between operation speed and ON current.
2Speed
If the gate electrode and source/drain electrode are spaced apart to reduce parasitic capacitance, then operation speed improves, but the distance between gate and drain increases
Solution Approach 1:
The offset gate electrode is positioned in a different spatial dimension (offset region) relative to the main gate electrode, allowing the structure to reduce parasitic capacitance through spatial separation rather than increasing the linear distance between gate and drain electrodes. This dimensional approach resolves the contradiction by utilizing lateral offset positioning.
3Reliability
If auxiliary gate electrodes are added to improve electric characteristics, then ON characteristics improve, but device complexity increases
Solution Approach 1:
The main gate electrode and offset gate electrode are formed using the same gate electrode layer material and are integrated into a unified gate structure. This merging approach reduces manufacturing complexity compared to adding separate auxiliary electrodes, while still achieving improved ON characteristics through the dual-electrode configuration.
Data Source
AI summary
A semiconductor device includes a first thin film transistor (101) on a substrate (10), the first thin film transistor including: a sub-gate electrode (12); a first insulating layer (14) covering the sub-gate electrode; a main gate electrode (16) formed on the first insulating layer; a second insulating layer (18) covering the main gate electrode; an oxide semiconductor layer (20) having a layered structure of a first layer (20A) and a second layer (20B), the second layer having a larger band gap than the first layer; a first source electrode (22); and a first drain electrode (24), wherein as seen from a direction normal to the substrate, the oxide semiconductor layer (20) includes: a gate opposing region (20g) that overlaps the main gate electrode; a source contact region that is in contact with the first source electrode (22); a drain contact region that is in contact with the first drain electrode; and an offset region (30s, 30d) that is provided at least one of between the gate opposing region and the source contact region and between the gate opposing region and the drain contact region, wherein at least a portion of the offset region overlaps the sub-gate electrode (12) with the first insulating layer (14) and the second insulating layer (18) therebetween.