Oxide Semiconductor TFT With Reduced Resistance Regions
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Solution Overview
Problem
Thin film transistors using oxide semiconductor films face a high probability of short-circuit when the channel width is increased to reduce parasitic capacitance, leading to a low yield rate in display apparatus applications.
Innovation Solution
A semiconductor device configuration where the gate electrode and source/drain electrodes do not overlap, with adjacent regions processed for reduced resistance, maintaining on-state current while minimizing parasitic capacitance and channel width, typically below 50 μm, using oxide semiconductor films like In-Ga-Zn-O.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the channel width of the thin film transistor is increased to reduce parasitic capacitance, then the parasitic capacitance is reduced, but the probability of short-circuit in the TFT increases
Solution Approach 1:
The invention applies different resistance characteristics to different regions of the oxide semiconductor film. Specifically, the channel region maintains high purity and high resistance to ensure proper transistor operation, while the source and drain regions are intentionally made low-resistance through additional processing steps. This local differentiation allows the transistor to achieve low parasitic capacitance with a narrow channel width while maintaining reliable electrical contact in the source and drain regions, thereby reducing short-circuit probability without increasing channel width.
2Object-affected harmful factors
If the channel width is increased to reduce parasitic capacitance, then the parasitic capacitance decreases, but the yield rate of the TFT decreases
Solution Approach 1:
The invention changes the resistance parameter of the oxide semiconductor film in specific regions through selective processing. By applying different treatments (such as different annealing conditions or additional deposition steps) to the source and drain regions compared to the channel region, the resistance is reduced in the contact regions while maintaining high resistance in the channel. This parameter change allows the use of narrow channel widths (reducing parasitic capacitance) while ensuring adequate current flow through the low-resistance source and drain regions, thereby improving yield rate.
3Power
If the channel width is significantly increased for buffer circuit TFTs to handle larger currents, then the current handling capability is improved, but the short-circuit probability increases significantly
Solution Approach 1:
For buffer circuit TFTs requiring high current handling capability, the invention extends the local quality principle by creating extended low-resistance regions in the source and drain areas. These low-resistance regions are formed through selective processing that reduces resistance only in the contact areas, allowing the channel width to remain narrow for reliability while the expanded low-resistance source and drain regions provide the necessary current handling capability for high-power buffer circuits.
Data Source
AI summary
A semiconductor device (ST) includes a substrate (11), a gate electrode (12b), a gate insulating film (13b), an oxide semiconductor film (14b) including a channel part (14bc) formed in a position facing the gate electrode (12b), a source electrode (15bs), and a drain electrode (15bd). The source electrode (15bs) and the drain electrode (15bd) is arranged so as not to overlap with the gate electrode (12b) as viewed in the plane. A region adjacent to the gate electrode (12b) and the source electrode (15bs) and a region adjacent to the gate electrode (12b) and the drain electrode (15bd) are, in a region where the source electrode (15bs) and the drain electrode (15bd) does not overlap with the gate electrode (12b), processed such that resistance in a region of the oxide semiconductor film (14b) including a surface thereof is reduced.