Three-Layer Oxide Semiconductor TFT Channel Structure
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Solution Overview
Problem
The challenge is to achieve a semiconductor device with an oxide semiconductor TFT that has stable characteristics and high reliability, as existing two-layer channel structure TFTs often exhibit varying threshold voltages and reliability issues due to mismatched crystal lattices and processability problems.
Innovation Solution
A three-layer channel structure is introduced, comprising a first and second crystalline oxide semiconductor layer with an amorphous intermediate layer, where the atomic ratios of In to Zn differ in each layer, and the intermediate layer maintains an amorphous state, improving the interface between the crystalline layers and preventing constricted parts during patterning, thus enhancing processability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a two-layer channel structure TFT with crystalline oxide semiconductor layers is used, then high mobility is achieved, but threshold voltage varies and reliability deteriorates due to crystal lattice mismatch
Solution Approach 1:
An amorphous oxide semiconductor layer is introduced as an intermediate layer between two crystalline oxide semiconductor layers. This intermediate layer acts as a buffer that prevents crystal lattice mismatch from causing threshold voltage variation, while still allowing the outer crystalline layers to provide high carrier mobility. The amorphous layer absorbs the stress and mismatch that would otherwise propagate between the crystalline layers.
Solution Approach 2:
The semiconductor layer is constructed as a composite structure combining amorphous and crystalline oxide semiconductor materials. The crystalline layers (with higher In atomic ratio) provide high mobility, while the amorphous intermediate layer (with balanced In and Zn atomic ratios) provides stability. This composite structure leverages the advantages of both material states to achieve both high speed and reliability.
2Speed
If a two-layer channel structure TFT is used, then high mobility is achieved, but processability deteriorates due to constricted parts forming during patterning
Solution Approach 1:
The amorphous oxide semiconductor intermediate layer serves as a mediator that prevents constricted parts from forming during the patterning process. When etching is applied, the amorphous layer etches more uniformly than directly interfacing crystalline layers, preventing the formation of constricted parts that would compromise processability and lead to film residue.
3Speed
If crystalline oxide semiconductor layers with different compositions are laminated, then high mobility is achieved, but film residue and process damage occur
Solution Approach 1:
The amorphous oxide semiconductor layer acts as a protective intermediary between the two crystalline layers during manufacturing processes. It prevents direct interaction between the crystalline layers that would cause film residue and process damage, while still allowing the crystalline layers to maintain their high mobility characteristics.
Solution Approach 2:
The amorphous intermediate layer is placed beforehand between the crystalline layers to cushion and absorb the effects of manufacturing stresses, etching variations, and thermal expansion differences. This preventive measure stops film residue and process damage before they can occur.
Data Source
AI summary
A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer is arranged nearer to the gate insulating layer than the second oxide semiconductor layer.