Double Gate Oxide Semiconductor Transistor Threshold Stability
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Solution Overview
Problem
In the manufacturing of thin film transistors with a double gate structure, the threshold voltage varies negatively when the top gate electrode is formed at the same location as the bottom gate electrode, posing a challenge in maintaining consistent electrical performance.
Innovation Solution
A display device with an active matrix substrate is designed, featuring a layered structure including a base insulating film, a first metal layer for the bottom gate electrode, a metal oxide layer, an inorganic insulating film, an oxide semiconductor layer, a second inorganic insulating film, a second metal layer for the top gate electrode, and a third metal layer for source and drain electrodes. The first bottom gate electrode overlaps with the oxide semiconductor layer through the metal oxide layer, and the metals used in the layers are distinct, ensuring proper electrical connections and reduced threshold voltage variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the top gate electrode is formed at the same location as the bottom gate electrode in a double gate structure, then the transistor can be manufactured, but the threshold voltage varies in a negative direction
Solution Approach 1:
An anodic oxide film is formed between the bottom gate electrode and the oxide semiconductor layer to serve as an intermediary layer. This film prevents direct contact between the bottom gate electrode and the oxide semiconductor, thereby suppressing negative threshold voltage variations while maintaining the double gate structure configuration
Solution Approach 2:
The physical and chemical parameters of the interface between the bottom gate electrode and oxide semiconductor are changed by forming an anodic oxide film. This alters the electrical characteristics at the interface, preventing harmful interactions and stabilizing the threshold voltage
Data Source
AI summary
A display device includes an active matrix substrate, wherein the active matrix substrate is layered with a base insulating film, a first metal layer, a metal oxide layer, a first inorganic insulating film, an oxide semiconductor layer, a second inorganic insulating film, a second metal layer, an interlayer insulating layer, and a third metal layer in order from a lower layer, and the active matrix substrate includes a first transistor configured of a first bottom gate electrode, a top gate electrode, and a source electrode and a drain electrode formed by the third metal layer, the source electrode and the drain electrode are respectively electrically connected to a source region and a drain region of the oxide semiconductor layer, the first bottom gate electrode is overlapped with the oxide semiconductor layer, and a metal of the first metal layer is different from a metal of the metal oxide layer.