Oxide Semiconductor Transistor Parasitic Capacitance Reduction
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Solution Overview
Problem
Miniaturization of transistors leads to increased parasitic capacitance, which reduces responsiveness and reliability of semiconductor devices, and introduces manufacturing process variations, making it difficult to control film formation and processing steps effectively.
Innovation Solution
A method for manufacturing semiconductor devices that involves depositing oxide insulating and semiconductor layers, forming island shapes, and performing heat treatment to create low-resistance regions with specific conductive layers, reducing parasitic capacitance and improving electrical characteristics by using elements like cobalt, nickel, and titanium, and forming a structure with a gate electrode that surrounds the oxide semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are miniaturized to achieve high integration, then productivity and integration density are improved, but parasitic capacitance increases and manufacturing precision deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the physical and chemical properties of the oxide semiconductor layer through controlled oxygen vacancy formation and heat treatment processes. By adjusting oxygen concentration, heat treatment temperature, and duration, the electrical characteristics and parasitic capacitance of the miniaturized transistor are optimized to maintain performance at smaller dimensions
Solution Approach 2:
The patent implements local quality by creating specific regions with different oxygen concentrations within the oxide semiconductor layer. Low-resistance regions with controlled oxygen vacancies are formed in specific locations to reduce parasitic capacitance locally, while maintaining appropriate characteristics in other regions of the transistor structure
2Productivity
If transistors are miniaturized, then integration density is improved, but parasitic capacitance increases reducing responsiveness
Solution Approach 1:
The patent changes physical parameters of the oxide semiconductor by controlling oxygen vacancy concentration through heat treatment. This modifies the electrical resistance and capacitance characteristics, enabling faster charging/discharging of parasitic capacitance and improving transistor responsiveness despite miniaturization
Solution Approach 2:
The patent replaces conventional semiconductor material systems with oxide semiconductor materials that exhibit different physical mechanisms. The oxide semiconductor's unique properties, including controllable oxygen vacancies and phase transitions, substitute for traditional silicon-based mechanisms to achieve lower parasitic capacitance effects at scaled dimensions
3Ease of manufacture
If conventional semiconductor materials are used, then manufacturing process is simple, but oxygen vacancies and interface states increase reducing reliability
Solution Approach 1:
The patent uses composite material structures combining oxide insulating layers with oxide semiconductor layers. This composite approach allows the oxide semiconductor to provide low-resistance channels with controlled oxygen vacancies, while the oxide insulating layers provide stable interfaces, collectively improving reliability without significantly complicating the manufacturing process
Solution Approach 2:
The patent applies preliminary action by performing heat treatment processes before final device assembly to pre-form and stabilize oxygen vacancy distributions in the oxide semiconductor layer. This preliminary oxygen concentration control reduces interface states and stabilizes electrical characteristics before subsequent manufacturing steps, improving reliability proactively
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance, enhances high-speed operation, and improves the reliability and electrical characteristics of semiconductor devices by minimizing oxygen vacancies and interface states, allowing for simpler manufacturing processes and lower power consumption.
Implementation Method 1
An element contained in the second conductive layer moves from the second conductive layer to the second oxide semiconductor layer side by performing the heat treatment
Implementation Method 2
depositing a first insulating layer over a substrate; sequentially depositing a first oxide insulating layer and a first oxide semiconductor layer
Data Source
AI summary
A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment. An element contained in the second conductive layer moves from the second conductive layer to the oxide semiconductor layer side by performing the heat treatment. An element contained in the oxide semiconductor layer moves from the oxide semiconductor layer to the third conductive layer side by performing the heat treatment.