Oxide Semiconductor Device Merging Transistor and Capacitor Structures

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Solution Overview

Problem

Semiconductor devices with oxide semiconductor channels face challenges in manufacturing complexity and cost due to the need for multiple masks and stacked films, particularly in forming capacitor elements with MIM structures, which increases costs and reduces yield.

Innovation Solution

A semiconductor device structure incorporating an n-type or p-type oxide semiconductor layer with a gate electrode and insulation layer, where the potential applied to terminals is controlled to maintain charge, allowing for a simpler structure and reduced resistance in the oxide semiconductor regions, thereby enabling low manufacturing costs and improved yield by sharing the same structure for both transistor and capacitor elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a MIM structure capacitor element is formed with metal layers and insulation layers, then capacitance function is achieved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvecapacitance functionVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the capacitor element structure with the transistor structure by using the gate electrode and gate insulation layer of the transistor as common components for both the transistor and capacitor functions. This eliminates the need for separate metal layers and insulation layers that would be required for a traditional MIM capacitor, thereby reducing manufacturing complexity while maintaining the capacitance function.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate electrode and gate insulation layer serve dual purposes: they function as the gate structure for the transistor and simultaneously as one of the electrodes and dielectric for the capacitor element. This multi-functionality reduces the total number of components and manufacturing steps required.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple masks and stacked thin films are used for capacitor element formation, then capacitance function is achieved, but manufacturing yield decreases

Engineering Contradiction:
Improvecapacitance functionVSAvoidmanufacturing yield
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines the capacitor formation process with the existing transistor formation process. By using the gate electrode and gate insulation layer that are already formed during transistor manufacturing, the need for additional masks and stacked thin films is eliminated, thereby improving manufacturing yield.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If oxide semiconductor layer has regions with different resistances, then charge storage capability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecharge storage capabilityVSAvoidresistance control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating regions with different resistance characteristics within the oxide semiconductor layer. Specifically, the gate electrode region has different resistance properties compared to other regions, allowing for optimized charge storage capability in different areas of the device.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10269977B2Semiconductor device including oxide semiconductor layer having regions with different resistances
Publication Date: 2019.04.23 MAGNOLIA WHITE CORP
  • US10269977B2 patent drawing
  • US10269977B2 patent drawing
  • US10269977B2 patent drawing

AI summary

A semiconductor device includes an n-type oxide semiconductor layer, a gate electrode above the oxide semiconductor layer, a gate insulation layer between the oxide semiconductor layer and the gate electrode, a first terminal connected to the oxide semiconductor layer, and a second terminal connected to the gate electrode, a potential applied to the second terminal being higher than a potential applied to the first terminal.