Oxide Semiconductor Transistor CMP Electrode Formation
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Solution Overview
Problem
As transistors are miniaturized, they face issues such as deterioration in electric characteristics, increased variation in threshold voltages, and higher off-state current, leading to reduced yield and reliability due to dry etching and impurity diffusion, making it challenging to achieve high-speed operation and low power consumption.
Innovation Solution
A semiconductor device structure with an oxide semiconductor layer, gate insulating layer, and sidewall insulating layers is developed, where a dopant is introduced using a self-aligned process to form low-resistance regions, and a chemical mechanical polishing method is used to form source and drain electrode layers without etching treatment, along with cleaning and oxygen supply treatments to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are miniaturized to achieve high-speed operation and low power consumption, then transistor size is reduced, but electric characteristics deteriorate and off-state current increases
Solution Approach 1:
The patent applies local quality by forming a crystalline oxide semiconductor layer with specific crystal orientations (c-axis or a-axis) in the channel formation region. This localized crystalline structure with specific orientation provides high mobility for fast operation while the self-aligned dopant introduction creates localized low-resistance regions that maintain stable electric characteristics and reduce off-state current, resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent changes physical parameters by controlling the crystal orientation (c-axis or a-axis) of the oxide semiconductor layer and adjusting dopant concentration in specific regions. These parameter changes enable the transistor to achieve high-speed operation through optimized charge carrier mobility while maintaining stable threshold voltage and reduced off-state current through controlled doping profiles.
2Productivity
If transistors are miniaturized, then device size is reduced, but variation in threshold voltage increases
Solution Approach 1:
The patent applies preliminary action by introducing dopants into the oxide semiconductor layer before forming the gate electrode, using the gate electrode itself as a mask for self-aligned dopant introduction. This preliminary doping action creates consistent low-resistance regions that stabilize threshold voltage across miniaturized devices, reducing variation while enabling further miniaturization.
Solution Approach 2:
The gate electrode serves a dual function: as the functional gate component and as a mask for self-aligned dopant introduction. This self-service approach ensures precise and uniform dopant placement relative to the gate, reducing threshold voltage variation in miniaturized transistors while maintaining manufacturing feasibility.
3Productivity
If transistors are miniaturized, then transistor dimensions are reduced, but yield and reliability decrease due to dry etching damage and impurity diffusion
Solution Approach 1:
The patent extracts the harmful dry etching step from the manufacturing process by using a chemical mechanical polishing method instead to form the source and drain electrode layers. This removal of the damaging etching process prevents dry etching damage and impurity diffusion, enabling reliable miniaturized transistor fabrication while maintaining high yield.
Solution Approach 2:
The patent replaces the mechanical/chemical dry etching process with a chemical mechanical polishing method. This substitution eliminates the harsh etching conditions that cause damage to miniaturized structures and impurity diffusion, while still achieving precise formation of source and drain electrode layers, thereby improving reliability and yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a miniaturized transistor with improved on-state characteristics, high-speed operation, and stable electric characteristics, achieving high yield and reliability while reducing off-state current.
Implementation Method 1
the interlayer insulating layer and the conductive layer are cut (grinded or polished), so that the conductive layer over the gate electrode layer is removed. Accordingly, a source electrode layer and a drain electrode layer are formed. As the cutting (grinding or polishing) method, a chemical mechanical polishing (CMP) method can be preferably used.
Implementation Method 2
a dopant may be introduced into the oxide semiconductor layer by a self-aligned process in which the gate electrode layer is used as a mask
Data Source
AI summary
In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.