Self-Aligned Oxide Semiconductor Transistor Gate Insulating Layer Alignment
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Solution Overview
Problem
In the production of self-aligned oxide semiconductor thin film transistors, ensuring precise alignment and consistent distances between the gate electrode and the source and drain electrodes is challenging, leading to deteriorated high-frequency characteristics due to excessive parasitic capacitance.
Innovation Solution
A method involving the formation of a field-effect transistor with a gate electrode insulating layer, patterning to create contact electrodes, and an intermediate layer with through holes for precise alignment and connection of source and drain electrodes, ensuring consistent distances and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned process is used to form gate electrode and source/drain electrodes, then alignment precision is improved, but manufacturing difficulty increases due to inconsistent distances from gate electrode to source/drain electrodes
Solution Approach 1:
The patent introduces a gate electrode insulating layer as an intermediary element between the active layer and the gate electrode. This insulating layer serves as a reference structure that enables precise alignment and consistent spacing between the gate electrode and source/drain electrodes, solving the problem of inconsistent distances while maintaining manufacturing feasibility
Solution Approach 2:
The gate electrode insulating layer is formed in advance before the gate electrode and source/drain electrodes are created. This preliminary structure establishes the spacing and alignment references needed for subsequent electrode formation, ensuring consistent distances are achieved without requiring complex real-time alignment adjustments
2Reliability
If overlapped parts between gate electrode and source/drain electrodes are reduced to improve high-frequency characteristics, then parasitic capacitance is reduced, but alignment precision requirements increase
Solution Approach 1:
The gate electrode insulating layer acts as a mediator that defines the spacing between electrodes. By controlling the thickness and positioning of this insulating layer, the patent achieves precise control over the overlapped parts area, enabling reduced parasitic capacitance while maintaining manufacturable alignment tolerances
Solution Approach 2:
The patent controls the physical parameters of the gate electrode insulating layer (thickness, lateral dimensions) to precisely control the spacing and overlap between electrodes. By adjusting these parameters, the design achieves optimal balance between parasitic capacitance reduction and alignment precision requirements
Data Source
AI summary
This disclosure relates to a field-effect transistor and a production method thereof, an array substrate and a production method thereof, and a display panel. The production method comprises: forming an active layer on a substrate; forming a gate electrode insulating layer on the active layer to define a gate electrode area as well as a source electrode area and a drain electrode area located on two sides of the gate electrode area on the active layer; applying a gate electrode layer to cover surfaces of the active layer and the gate electrode insulating layer; patterning the gate electrode layer to form a first contact electrode, a second contact electrode, and a gate electrode, wherein the first contact electrode is located on the source electrode area, the second contact electrode is located on the drain electrode area, and the gate electrode is located on the gate electrode insulating layer.