Oxide Semiconductor Transistor with Graded Crystallinity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed transistors used in active matrix display devices have low reliability due to their operational limitations.
Innovation Solution
A transistor design featuring a semiconductor layer with multiple layers of varying crystallinity, where the ratio of crystalline to amorphous oxide semiconductor is higher in the uppermost layer compared to the lower layers, enhancing the transistor's speed and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a transistor is designed to operate at high speed, then the operating speed is improved, but the reliability deteriorates
Solution Approach 1:
The semiconductor layer is divided into multiple sub-layers with different crystallinities. The lower sub-layer has higher crystallinity for high-speed operation, while the upper sub-layer has lower crystallinity for improved reliability and interface quality. This local differentiation resolves the contradiction between speed and reliability by assigning different functional characteristics to different regions of the same component.
Solution Approach 2:
The invention uses a composite semiconductor layer structure combining crystalline and amorphous oxide semiconductor materials in specific proportions. The composite structure leverages the high mobility of crystalline regions for speed while the amorphous regions provide stability and reliability, thus resolving the trade-off between operating speed and device reliability.
2Speed
If the crystallinity of the semiconductor layer is increased to improve speed, then the operating speed is improved, but the manufacturing complexity increases
Solution Approach 1:
The semiconductor layer is segmented into multiple sub-layers with different crystallinity levels. This segmentation allows each sub-layer to be optimized independently for its specific function while simplifying the overall manufacturing process, as each layer can be formed using standard deposition techniques followed by controlled annealing to achieve the desired crystallinity gradient.
Solution Approach 2:
The invention controls the crystallinity parameter of the semiconductor layer by adjusting deposition conditions and annealing parameters. By changing these processing parameters, the desired multi-layer crystallinity structure can be achieved without significantly increasing manufacturing complexity, thus resolving the contradiction between speed performance and ease of manufacture.
Data Source
AI summary
A transistor includes a gate electrode, a semiconductor layer overlapping the gate electrode, the semiconductor layer including an oxide semiconductor, and a source electrode and a drain electrode spaced apart from the source electrode, wherein the source and drain electrodes are connected to the semiconductor layer. The semiconductor layer includes a plurality of layers, wherein a crystallinity of a layer of the plurality of layers of the semiconductor layer is a ratio of a crystalline oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer, to an amorphous oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer. A first layer of the plurality of layers of the semiconductor layer has a different crystallinity with respect to a second layer of the plurality of layers of the semiconductor layer.