Oxide Semiconductor Transistor Self-Aligned Low-Resistance Regions
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Solution Overview
Problem
Miniaturization of transistors is hindered by high contact resistance due to Schottky junctions at the interface between conductive and semiconductor layers, leading to reduced on-state current and field-effect mobility.
Innovation Solution
A semiconductor device structure with an oxide semiconductor layer, where a channel formation region and low-resistance regions are formed in a self-aligned manner using a gate electrode layer as a mask, and wiring layers are connected to these regions to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the transistor is miniaturized to achieve high-speed operation and low power consumption, then the transistor size is reduced, but the contact area between the semiconductor layer and conductive layer is reduced, causing contact resistance to increase significantly
Solution Approach 1:
The patent applies local quality by creating low-resistance regions with different impurity concentrations in specific areas of the oxide semiconductor layer. The channel formation region has a first impurity concentration while the low-resistance regions have a second impurity concentration higher than the first, optimizing both transistor action and contact properties in different locations.
Solution Approach 2:
The patent performs preliminary action by forming the low-resistance regions in the oxide semiconductor layer before forming the conductive layers. This self-aligned formation using the gate electrode layer as a mask ensures that the contact regions are prepared in advance with appropriate impurity concentrations to reduce contact resistance.
2Device complexity
If the contact resistance is increased due to Schottky junction formation, then the transistor structure is simpler, but the on-state current is reduced and field-effect mobility is decreased
Solution Approach 1:
The patent applies parameter changes by controlling the impurity concentration in the oxide semiconductor layer. The channel formation region has a first impurity concentration while the low-resistance regions have a second impurity concentration higher than the first, optimizing both transistor action and contact properties without changing the basic transistor structure.
3Object-affected harmful factors
If treatment for adding an impurity is performed with the use of a gate electrode layer as a mask to form low-resistance regions, then contact resistance is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies self-service by using the gate electrode layer as a self-aligned mask during impurity addition. The gate electrode layer automatically defines the boundaries of the low-resistance regions without requiring separate masking steps, simplifying the manufacturing process while achieving the desired impurity distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables favorable electric characteristics, miniaturization of transistors, reduced resistance between wiring and oxide semiconductor layers, and improved on-state current and mobility, leading to high-speed operation and lower power consumption.
Implementation Method 1
treatment for adding an impurity is performed on the oxide semiconductor layer with the use of a gate electrode layer as a mask
Data Source
AI summary
In a semiconductor device including an oxide semiconductor layer, a conductive layer is formed in contact with a lower portion of the oxide semiconductor layer and treatment for adding an impurity is performed, so that a channel formation region and a pair of low-resistance regions between which the channel formation region is sandwiched are formed in the oxide semiconductor layer in a self-aligned manner. Wiring layers electrically connected to the conductive layer and the low-resistance regions are provided in openings of an insulating layer.