Oxide Semiconductor Transistor With Multi-Layer Insulator
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Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization due to limitations in transistor scaling, leading to increased parasitic capacitance, reduced operation frequency, and unstable electrical characteristics, particularly with the short channel effect and variation in electrical characteristics as devices are miniaturized.
Innovation Solution
A transistor structure is developed with an oxide semiconductor where the channel is surrounded by an electric field from a gate conductor, featuring a unique configuration with multiple insulators and conductors to reduce parasitic capacitance and enhance control over the channel, allowing for miniaturization while maintaining stable electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If transistor size is reduced to achieve miniaturization, then device density increases, but parasitic capacitance increases and operation frequency decreases
Solution Approach 1:
The patent applies local quality by creating a multi-layer insulator structure with different dielectric constants positioned at specific locations around the channel. The first insulator with higher dielectric constant is positioned closer to the channel while the second insulator with lower dielectric constant is positioned farther away, optimizing the electric field distribution locally to reduce parasitic capacitance while maintaining channel control.
Solution Approach 2:
The patent transitions from a conventional planar gate structure to a three-dimensional multi-layer insulator configuration. By stacking insulators at different heights and positions around the channel, the invention creates a vertical dimension of control that reduces parasitic capacitance without increasing the horizontal footprint of the transistor.
2Ease of manufacture
If conventional insulator structures are used in miniaturized transistors, then manufacturing is simpler, but electrical characteristics become unstable due to short channel effect
Solution Approach 1:
The patent segments the insulator layer into multiple distinct layers with different dielectric constants, each positioned at specific locations around the channel. This segmentation allows independent optimization of each insulator layer's properties and position, enabling better electrical characteristics while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
The patent employs a composite insulator structure combining materials with different dielectric constants in a multi-layer configuration. This composite approach allows the system to leverage the advantages of different materials - high dielectric constant for strong field control near the channel and low dielectric constant for reduced parasitic capacitance farther from the channel.
Data Source
AI summary
An insulator is formed over a substrate, an opening is formed in the insulator, and an oxide semiconductor is formed in the opening. Then, part of the insulator is removed to expose a side surface of the oxide semiconductor.