Oxide Semiconductor Vertical Channel Structure for Fine Channel Length
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving a fine channel length due to resolution limitations in photolithography for planar devices and complexity in the process of forming vertical devices, making it difficult to miniaturize effectively.
Innovation Solution
A semiconductor device with a planar stack structure comprising two source/drain electrodes, a gate electrode layer in between, and an oxide semiconductor layer that penetrates through the gate electrode layer, utilizing a silicon-on-insulator substrate and indium-gallium-zinc oxide material, allowing for a simpler process to achieve a fine channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography is used for planar devices, then the manufacturing process is simple, but the channel length cannot be made small due to resolution limitation
Solution Approach 1:
The invention transitions from a planar two-dimensional structure to a vertical three-dimensional structure. The channel is formed vertically through the substrate with the gate electrode wrapping around it, allowing the channel length to be defined by the thickness of the gate dielectric layer rather than by photolithography resolution. This dimensional change enables sub-100nm channel lengths that are not achievable with conventional planar photolithography.
2Length of moving object
If vertical device structure is used, then the channel length can be made small, but the process becomes more complicated and contact formation is difficult
Solution Approach 1:
The invention segments the device into distinct functional layers: substrate, gate dielectric layer, gate electrode layer, and source/drain electrodes. Each layer is formed through separate, well-established deposition and etching processes. The gate dielectric layer is deposited conformally and then etched back to expose the substrate, creating a simplified vertical structure that avoids the complexity of forming contacts in fully three-dimensional vertical transistors.
Solution Approach 2:
The gate dielectric layer is deposited conformally over the entire substrate before any patterning occurs. This preliminary conformal deposition establishes the vertical channel structure and gate wrap-around geometry in advance, simplifying subsequent processing steps. The etch-back process then selectively removes excess material to create the final device structure.
3Reliability
If oxide semiconductor layer penetrates through gate electrode layer, then direct contact with source/drain electrodes is achieved, but additional layers and processes are required
Solution Approach 1:
The oxide semiconductor layer is deposited conformally to automatically fill the space between the source/drain electrodes and penetrate through the gate electrode layer. This self-aligned conformal deposition ensures that the semiconductor layer forms direct contact with the source/drain electrodes without requiring additional alignment steps or complex patterning processes. The material naturally conforms to the underlying topography, creating reliable electrical contact.
Data Source
AI summary
A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a first electrode layer disposed on the substrate, a gate electrode layer disposed on the first electrode layer, a second electrode layer disposed on the gate electrode layer, an oxide semiconductor layer penetrating through the gate electrode layer, a gate dielectric layer disposed between the gate electrode layer and the oxide semiconductor layer, a first insulating layer disposed between the gate electrode layer and the first electrode layer, and a second insulating layer disposed between the gate electrode layer and the second electrode layer. The oxide semiconductor layer is in direct contact with the first electrode layer and the second electrode layer, respectively.