Oxide Semiconductor Memory Circuit for Low Power Storage
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Solution Overview
Problem
Existing storage devices require complex manufacturing processes and high power consumption, especially when stopping the application of source voltage for short periods, as they rely on magnetic or ferroelectric nonvolatile memory circuits or external memory transfers, which are inefficient.
Innovation Solution
A storage device using a nonvolatile memory circuit with an oxide semiconductor transistor and a silicon transistor, allowing data to be written to the nonvolatile memory before voltage is stopped and read back when resumed, enabling operation across a wide frequency range with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a magnetic element or ferroelectric is used for the nonvolatile memory circuit, then data can be stored nonvolatibly, but the manufacturing process becomes complicated
Solution Approach 1:
The patent changes the material parameter from magnetic elements or ferroelectrics to oxide semiconductor transistors, achieving nonvolatile memory functionality while simplifying the manufacturing process. The oxide semiconductor transistor's extremely low off-state current enables data retention without requiring complex magnetic or ferroelectric material processing.
Solution Approach 2:
The patent replaces expensive and complex magnetic elements or ferroelectric materials with simpler, more readily manufacturable oxide semiconductor transistors. This substitution achieves similar nonvolatile storage functionality using more accessible and easier-to-manufacture components.
2Reliability
If data is transferred to an external memory circuit, then data can be preserved during voltage stop, but the process takes a long time
Solution Approach 1:
The patent divides the memory system into two segments: a volatile memory circuit ( latch circuit) for high-speed operation during normal use, and a nonvolatile memory circuit (oxide semiconductor transistor-based) for data retention during voltage stops. This segmentation allows each circuit to operate in its optimal mode without requiring full data transfer between them.
Solution Approach 2:
The patent introduces a switching circuit as an intermediary between the volatile latch circuit and the nonvolatile oxide semiconductor memory circuit. This switching circuit enables rapid data transfer between the two memory types, eliminating the need for slow external memory transfers while preserving data during voltage interruptions.
3Loss of energy
If the supply of source voltage is stopped, then power consumption is reduced, but data in volatile memory is lost
Solution Approach 1:
The patent prepares the system by implementing a nonvolatile memory circuit using oxide semiconductor transistors before voltage stoppage occurs. This preliminary setup ensures that data can be rapidly transferred to the nonvolatile circuit and preserved without loss, even during brief voltage interruptions for power saving.
Solution Approach 2:
The patent provides a safety cushion by implementing redundant data storage capability in the nonvolatile oxide semiconductor memory circuit. This cushioning mechanism ensures that even if voltage is stopped unexpectedly, data is protected from loss, allowing aggressive power-saving strategies to be employed.
Data Source
AI summary
The storage device includes a volatile first memory circuit and a nonvolatile second memory circuit which includes a transistor whose channel is formed in an oxide semiconductor layer. In the case of high-frequency driving, during a period when source voltage is applied, a data signal is input to and output from the first memory circuit, and during a part of a period when source voltage is supplied, which is before the supply of the source voltage is stopped, a data signal is input to the second memory circuit. In the case of low-frequency driving, during a period when source voltage is applied, a data signal is input to the second memory circuit, the data signal input to the second memory circuit is input to the first memory circuit, and the data signal input to the first memory circuit is output.