Oxide Semiconductor Connection Wire Aperture Ratio

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Solution Overview

Problem

The presence of contact holes in display devices reduces the aperture ratio, leading to decreased performance in information processing and display.

Innovation Solution

The use of an oxide semiconductor connection wire with lower sheet resistance, formed from the same oxide semiconductor material layer as the oxide semiconductor layer, which is integrated and connected to the layer, reducing the need for separate conductive wires and contact holes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If contact holes are formed to electrically connect signal wires at crossing regions, then electrical connectivity is achieved, but the aperture ratio of the display device is reduced

Engineering Contradiction:
Improveelectrical connectivityVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the oxide semiconductor layer with the connection wire by forming the connection wire from the same oxide semiconductor material layer. This integration eliminates the need for separate contact holes to connect the oxide semiconductor layer to the connection wire, as they become a continuous integrated structure. The merging of these components maintains electrical connectivity while removing the aperture-reducing contact holes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts and eliminates the contact holes from the display device structure by making the connection wire integrally connected to the oxide semiconductor layer. By taking out the unnecessary contact holes that were previously required for electrical connection, the aperture ratio is increased while electrical connectivity is maintained through the integrated oxide semiconductor structure.

Inventive Principle:
Principle #2Taking out (Extraction)

2Adaptability or versatility

If multiple separate components (oxide semiconductor layer and connection wire) are used, then functional flexibility is maintained, but device complexity and number of contact holes increase

Engineering Contradiction:
Improvefunctional flexibilityVSAvoidnumber of components and contact holes
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the oxide semiconductor layer and connection wire into a single integrated component formed from the same oxide semiconductor material layer. This merging reduces the total number of separate components and eliminates the contact holes needed to connect them, thereby reducing device complexity while maintaining the necessary electrical connection functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The oxide semiconductor material layer serves multiple functions simultaneously: it acts as the active oxide semiconductor layer for the transistor and as the connection wire for electrical connectivity. This multi-functionality eliminates the need for separate components and contact holes, reducing device complexity while maintaining functional flexibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10020324B2Display device
Publication Date: 2018.07.10 LG DISPLAY CO LTD
  • US10020324B2 patent drawing
  • US10020324B2 patent drawing
  • US10020324B2 patent drawing

AI summary

A disclosed display device includes a first oxide semiconductor layer and an oxide semiconductor connection wire both formed from an oxide semiconductor material layer over a substrate. The oxide semiconductor connection wire is integrally connected to the first oxide semiconductor layer and has a lower sheet resistance than the first oxide semiconductor layer. The display device also includes a first gate electrode either over the first oxide semiconductor layer or between the first oxide semiconductor layer and the substrate. The display device further includes a first gate insulation layer between the first oxide semiconductor layer and the first gate electrode.