Oxide Semiconductor Layer Structure for Lower Wiring Resistance
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving favorable electrical characteristics and high reliability, particularly in large-screen, high-definition display devices where increased wiring resistance is a concern.
Innovation Solution
A semiconductor device structure is developed with a specific layer configuration including a semiconductor layer, insulating layers, a metal oxide layer, and a conductive layer, where the layers are stacked with tapered ends and a functional layer to manage resistance and adhesion, reducing wiring resistance and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the screen size and definition are increased, then the display performance is improved, but the wiring resistance increases
Solution Approach 1:
The patent applies local quality by creating distinct regions within the semiconductor layer with different resistance characteristics. Specifically, it forms a first region (channel formation region) and second regions (source/drain regions) with different impurity concentrations and resistance values, optimizing each region's electrical properties for its specific function while addressing the overall wiring resistance issue in large-screen displays
Solution Approach 2:
The patent employs parameter changes by varying the impurity concentration, thickness, and material composition across different regions of the semiconductor layer. The channel formation region has lower impurity concentration for high mobility, while source/drain regions have higher impurity concentration for low resistance, thereby resolving the wiring resistance problem in large-screen displays
2Reliability
If oxide semiconductor layers are stacked to increase field-effect mobility, then the transistor performance is improved, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor layer into multiple functional regions (channel formation region and source/drain regions) with distinct electrical properties. This segmentation allows each region to be optimized independently for its specific function, achieving high field-effect mobility in the channel while maintaining low resistance in source/drain regions, thereby improving transistor performance without excessive complexity
Solution Approach 2:
The patent employs multi-functionality by using a single semiconductor layer that simultaneously performs multiple functions: forming high-mobility channels for transistor operation and providing low-resistance source/drain regions for current conduction. This is achieved through lateral variation in impurity concentration and thickness within the same layer, eliminating the need for separate stacked layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure achieves favorable electrical characteristics and high reliability by optimizing resistance and adhesion, thereby improving the performance of semiconductor devices in large-screen, high-definition display applications.
Implementation Method 1
A metal oxide that can be used for a semiconductor layer can be formed by a sputtering method or the like
Data Source
AI summary
A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a metal oxide layer, and a conductive layer; the first insulating layer, the metal oxide layer, and the conductive layer are stacked in this order over the semiconductor layer; an end portion of the first insulating layer is located inward from an end portion of the semiconductor layer; an end portion of the metal oxide layer is located inward from the end portion of the first insulating layer; and an end portion of the conductive layer is located inward from the end portion of the metal oxide layer. The second insulating layer is preferably provided to cover the semiconductor layer, the first insulating layer, the metal oxide layer, and the conductive layer. It is preferable that the semiconductor layer include a first region, a pair of second regions, and a pair of third regions; the first region overlap with the first insulating layer and the metal oxide layer; the second regions between which the first region is sandwiched overlap with the first insulating layer and not overlap with the metal oxide layer; the third regions between which the first region and the pair of second regions are sandwiched not overlap with the first insulating layer; and the third regions be in contact with the second insulating layer.