Semiconductor Memory Cell Using Oxide Semiconductor Write Transistor
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in data retention, power consumption, and durability due to high off-state current and the need for frequent refresh operations in volatile memories, and the degradation of gate insulating layers in non-volatile flash memories, especially when data is frequently rewritten.
Innovation Solution
A semiconductor device with a non-volatile memory cell using a write transistor with an oxide semiconductor and a read transistor with a different semiconductor material, allowing for long-term data retention without refresh operations, reduced power consumption, and high durability by eliminating the need for high voltage charge injection and minimizing gate insulating layer deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a volatile memory device (DRAM) is used to store data, then writing and reading operations can be performed quickly, but charge is lost when data is read out requiring frequent refresh operations and power consumption cannot be adequately reduced
Solution Approach 1:
The invention divides the memory system into two distinct transistor components: a first transistor for charge storage with minimal leakage, and a second transistor for read/write operations. This segmentation allows each component to be optimized for its specific function, resolving the contradiction between speed and power consumption.
Solution Approach 2:
Different semiconductor materials are used for different parts of the memory cell. The first transistor uses a material optimized for low off-state current (such as oxide semiconductor), while the second transistor uses a material optimized for switching speed. This local differentiation of material properties resolves the contradiction between retention and speed.
2Speed
If a volatile memory device (DRAM or SRAM) is used, then fast access is achieved, but stored data is lost when power supply stops requiring another memory device for long-term data holding
Solution Approach 1:
The memory cell is segmented into two transistors with different functions: the first transistor is optimized for data retention with extremely low off-state current, while the second transistor handles access operations. This segmentation enables both fast access and reliable data retention without power.
Solution Approach 2:
The invention uses composite semiconductor materials - combining materials with different properties (e.g., oxide semiconductor for low leakage, silicon-based material for high mobility) in different transistor components within the same memory cell, achieving both retention and speed.
3Duration of action of stationary object
If a non-volatile memory device (flash memory) is used to achieve long data holding period and eliminate refresh operations, then the gate insulating layer deteriorates due to tunneling current generated in writing operations
Solution Approach 1:
The invention changes the operating parameters of the memory cell by using a first transistor with extremely low off-state current characteristics. This parameter change enables long-term charge storage without the need for high-voltage tunneling operations that cause gate insulating layer deterioration in flash memory.
4Duration of action of stationary object
If flash memory is used to store data with long holding period, then high voltage is necessary for holding charge or removing charge and a circuit therefor is required
Solution Approach 1:
The invention changes the voltage parameter requirements by using a first transistor with minimal leakage current. This enables charge storage at standard voltages without requiring high-voltage generation circuits, thereby reducing device complexity while maintaining long data holding capability.
5Duration of action of stationary object
If flash memory is used to inject or remove electric charge, then it takes a relatively long time and it is not easy to increase a speed of writing and erasing data
Solution Approach 1:
The memory cell is segmented into two transistors: the first transistor for charge storage and the second transistor for charge transfer operations. This segmentation enables fast writing and erasing through the second transistor while the first transistor maintains long charge holding capability, resolving the speed-retention contradiction.
Solution Approach 2:
The use of different semiconductor materials in the two transistors enables optimized performance for each function - the second transistor uses high-mobility material for fast switching during write/erase operations, while the first transistor uses low-leakage material for long-term charge storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves long-term data retention, low power consumption, and high durability by utilizing an oxide semiconductor with low off-state current and a separate read transistor for high-speed operation, eliminating the need for frequent refresh and reducing the risk of gate insulating layer degradation.
Implementation Method 1
a write transistor which includes an oxide semiconductor
Implementation Method 2
a capacitor
Data Source
AI summary
A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or rewritten to the memory cell by turning on the write transistor and applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another, and then turning off the write transistor so that the predetermined amount of charge is held in the node.