Oxide Semiconductor Sequential Circuit for Data Retention During Power Gating
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Solution Overview
Problem
In semiconductor integrated circuits, power gating to reduce power consumption can lead to data loss in storage circuits, requiring additional arithmetic operations when power is resumed, which increases power consumption and delays system restart.
Innovation Solution
Incorporating transistors with oxide semiconductor channels and capacitors to maintain node potentials during power gating, ensuring data integrity and reducing the need for additional arithmetic operations upon power resumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power gating is applied to reduce power consumption, then power consumption is reduced, but data is erased from storage circuits
Solution Approach 1:
The patent applies preliminary action by transferring data from storage circuits to temporary holding circuits before power gating is activated. This ensures data is preserved in a safe location before the power supply is cut off, preventing data loss while enabling power consumption reduction. The data transfer operation is completed in advance, so when power gating occurs, no data is lost.
Solution Approach 2:
The patent uses temporary holding circuits as intermediary storage between the main storage circuits and the power gating mechanism. These holding circuits act as a buffer that maintains data during the power transition, mediating between the need to preserve data and the need to reduce power consumption. The intermediary holding circuits are designed to retain data with minimal power or in a floating state.
2Use of energy by moving object
If power gating is applied to reduce power consumption, then power consumption is reduced, but additional arithmetic operations are required upon power resumption
Solution Approach 1:
The patent performs data transfer to holding circuits as a preliminary action before power gating, so that upon power resumption, the main storage circuits are already prepared and no additional arithmetic operations are needed. This preliminary preparation eliminates the time delay that would otherwise occur during system restart.
Solution Approach 2:
The patent discards the need for redundant arithmetic operations by recovering data from the holding circuits directly into the storage circuits upon power resumption. This recovery process is optimized to be faster than performing full arithmetic operations, thereby reducing restart delay while maintaining data integrity.
3Use of energy by moving object
If power gating is applied to reduce power consumption, then power consumption is reduced, but system operation is delayed
Solution Approach 1:
The patent executes data transfer to holding circuits as a preliminary action before power gating activates. This advance preparation ensures that when power is restored, the system can resume operation immediately without performance degradation, thus maintaining productivity while still achieving power consumption reduction during idle periods.
Solution Approach 2:
The patent implements periodic data synchronization between storage circuits and holding circuits. By periodically updating the holding circuits with current data before power gating events, the system ensures that resumption occurs with minimal delay, maintaining operational productivity while enabling power savings during low-activity periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and operational delays by maintaining data integrity and eliminating the need for redundant arithmetic operations during power cycling.
Implementation Method 1
The oxide semiconductor has a band gap wider than silicon and an intrinsic carrier density lower than silicon
Implementation Method 2
The oxide semiconductor has a band gap wider than silicon and an intrinsic carrier density lower than silicon
Implementation Method 3
a capacitor whose one electrode is electrically connected to a node that is brought into a floating state when the transistor is turned off
Data Source
AI summary
Provided is a semiconductor device including a sequential circuit including a first transistor and a capacitor. The first transistor includes a semiconductor layer including indium, zinc, and oxygen to form a channel formation region. A node electrically connected to a source or a drain of the first transistor and a capacitor becomes a floating state when the first transistor turns off, so that a potential of the node can be maintained for a long period. A power-gating control circuit may be provided to control supply of power supply potential to the sequential circuit. The potential of the node still can be maintained while supply of the power supply potential is stopped.