Oxide-Silicon Shift Register for Stable Display Gate Signals

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Solution Overview

Problem

Existing shift registers in display technologies suffer from signal instability and circuit logic errors due to deviations in output signal stability, leading to drive anomalies.

Innovation Solution

A shift register design incorporating a node control module, voltage stabilizing modules, and a protection module to ensure opposite potentials between nodes, preventing signal interference and dangling points, using transistors with oxide and silicon active layers for enhanced stability and reduced transistor count.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional shift register architecture is used, then device complexity is reduced, but output signal stability deteriorates

Engineering Contradiction:
Improveoutput signal stabilityVSAvoidcircuit architecture complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-establishing opposite potential relationships between node pairs (first node and third node, second node and fourth node) before signal transmission occurs. The voltage stabilizing modules are configured to maintain these opposite potential states in advance, ensuring that when signals are transmitted through the shift register, the output signals remain stable and free from deviations that would cause circuit logic errors.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple cascaded shift registers are used, then drive signal transmission capability is improved, but signal stability deteriorates

Engineering Contradiction:
Improvedrive signal transmission capabilityVSAvoidsignal stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms through voltage stabilizing modules that continuously monitor and maintain the potential relationships between node pairs. In the cascaded shift register configuration, each stage provides feedback to ensure its output nodes maintain opposite potentials, which stabilizes the signal as it propagates through multiple stages of the cascaded architecture, preventing signal degradation over long transmission distances.

Inventive Principle:
Principle #23Feedback

3Reliability

If additional voltage stabilizing modules are added, then signal stability is improved, but device complexity increases

Engineering Contradiction:
Improvecircuit stabilityVSAvoidmodule quantity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the voltage stabilization function into separate, dedicated modules that are selectively applied to specific node pairs within the shift register. Rather than making the entire circuit complex, only the essential nodes (first, second, third, and fourth nodes) that require potential stabilization are equipped with voltage stabilizing modules. This targeted approach maintains circuit stability while avoiding unnecessary complexity in non-critical areas.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP4290507B1Shift register, gate driver circuit, display panel, and electronic device
Publication Date: 2025.10.22 HONOR DEVICE CO LTD
  • EP4290507B1 patent drawingFigure 1~2
  • EP4290507B1 patent drawingFigure 3
  • EP4290507B1 patent drawingFigure 4

AI summary

This application provides a shift register, a gate drive circuit, a display panel, and an electronic device. The shift register includes a node control module, electrically connected to a first level signal receiving end, a second level signal receiving end, a first node, and a second node; an input module, electrically connected to a first clock signal end, a trigger signal input end, and the second node; an output module, electrically connected to the first level signal receiving end, the second level signal receiving end, the first node, a third node, and a drive signal output end; a first voltage stabilizing module, electrically connected to the first node, a fourth node, and the second level signal receiving end; and a second voltage stabilizing module, electrically connected to the second node, the third node, the fourth node, and a second clock signal end.