Oxide Spacer Layer for Gate Cut Critical Dimension Control

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Solution Overview

Problem

Critical dimension control and robust etch processes during the gate cut module in FinFET manufacturing remain challenging, especially in forming sacrificial gate structures that can be replaced without affecting downstream processing, including conductive contacts to source/drain and gate structures.

Innovation Solution

A method involving the deposition of an oxide spacer layer after an etch step that exposes the sacrificial gate, which facilitates precise definition of the gate cut opening and backfills recessed regions, allowing for accurate segmentation of the sacrificial gate in the replacement metal gate (RMG) process flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional gate cut processes are used, then sacrificial gate segmentation can be achieved, but critical dimension control and etch robustness remain challenging

Engineering Contradiction:
Improvecritical dimension controlVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The gate cut process is segmented into multiple controlled steps: forming opening in hard mask, depositing oxide spacer layer, then etching sacrificial gate. This segmentation allows independent optimization of each step, improving critical dimension control while managing overall process complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The oxide spacer layer is deposited preliminarily before the sacrificial gate etch step. This preliminary action establishes precise critical dimensions for the gate cut opening, ensuring accurate segmentation while simplifying the subsequent etch process.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If precise gate cut is achieved, then accurate sacrificial gate segmentation is enabled, but downstream processing including conductive contact formation may be adversely affected

Engineering Contradiction:
Improvegate cut accuracyVSAvoiddownstream processing reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The oxide spacer layer acts as an intermediary between the hard mask opening and the sacrificial gate etch. It mediates the critical dimension transfer while protecting adjacent regions, ensuring both accurate gate cut and compatibility with downstream conductive contact formation processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The oxide spacer layer provides locally differentiated properties: it defines precise critical dimensions at the gate cut location while simultaneously backfilling recessed regions adjacent to the sacrificial gate, creating different local conditions optimized for different downstream processes.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If oxide spacer layer is deposited after etch step, then critical dimension control is improved, but process sequence complexity increases

Engineering Contradiction:
Improvecritical dimension definitionVSAvoidprocess sequence complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The oxide spacer layer deposition step serves multiple functions simultaneously: it defines critical dimensions, backfills recessed regions, and prepares the surface for downstream processing. This self-service approach improves precision while minimizing the need for additional separate process steps.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables precise control of critical dimensions in gate cut openings, ensuring accurate segmentation of sacrificial gates and facilitating robust downstream processing, including the formation of conductive contacts, thereby improving device density and performance.

Implementation Method 1

An oxide spacer layer is formed within the recessed region

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

An oxide spacer layer is formed within the recessed region

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

An etching step is used to form an opening in the hard mask, which exposes a top surface of the sacrificial gate and creates a recessed region within the interlayer dielectric

Methodology Applied
Scientific EffectReactive Ion Etching: Plasma

Implementation Method 4

the sacrificial gate is etched to form a gate cut opening that extends through the sacrificial gate between an adjacent pair of the fins

Methodology Applied
Scientific EffectSelective Etching: Plasma

Data Source

PatentUS10396206B2Gate cut method
Publication Date: 2019.08.27 GLOBALFOUNDRIES US INC
  • US10396206B2 patent drawing
  • US10396206B2 patent drawing
  • US10396206B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.