Oxide Spacer Reduces Parasitic Capacitance in Stack DRAM
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Solution Overview
Problem
The use of silicon nitride as a spacer in stack DRAM manufacturing results in higher parasitic capacitance, interfering with circuit efficiency and quality due to its higher dielectric constant.
Innovation Solution
A method involving a semiconductor base with oxide, word line stacks, and polysilicon, where a multi-layer resist coat is applied, lithography and etching form contact holes, an oxide layer is deposited and etched to create spacers, and polysilicon is used to form capacitor contacts, reducing parasitic capacitance by employing an oxide layer instead of silicon nitride.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride is used as the spacer, then the spacer can be formed successfully, but the parasitic capacitance increases due to higher dielectric constant
Solution Approach 1:
The patent changes the material parameter (dielectric constant) by replacing silicon nitride with oxide material, thereby reducing parasitic capacitance while maintaining spacer formation functionality through process parameter optimization
Solution Approach 2:
The patent introduces an intermediary oxide layer between the bit line and underlying structures, which acts as a spacer with lower dielectric constant to reduce parasitic capacitance while still providing the necessary electrical isolation
2Object-generated harmful factors
If oxide layer is used instead of silicon nitride, then parasitic capacitance is reduced, but additional process steps are required
Solution Approach 1:
The patent combines the oxide layer deposition with existing manufacturing steps, integrating the low-parasitic-capacitance spacer formation into the standard bit line fabrication process flow to minimize additional process complexity
Solution Approach 2:
The oxide layer serves multiple functions: it acts as a spacer for electrical isolation, provides a low-parasitic-capacitance interface, and can be integrated with existing dielectric layers in the stack DRAM structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, improving the efficiency and quality of stack DRAM operations by utilizing an oxide layer with a lower dielectric constant, compatible with the original manufacturing method.
Implementation Method 1
depositing an oxide layer
Implementation Method 2
applying a multi layer resist coat onto the upper surface of the semiconductor base
Data Source
AI summary
A method of manufacturing low parasitic capacitance bit line for stack DRAM, comprising the following steps: offering a semi-conductor base, which semi-conductor having already included an oxide, plural word line stacks, plural bit line stacks and plural polysilicons; applying a multi layer resist coat; removing the multi layer resist coat and further removing parts of the oxide located on the polysilicon to form contact holes exposing the plural polysilicons; depositing an oxide layer; etching the oxide layer to form the oxide layer spacer; depositing a polysilicon layer; performing lithography and etching on the polysilicon layer thereby allowing the rest of the polysilicon layer that is column-shaped to form capacitor contacts; and using another oxide to fill into the space among the word line stacks and the capacitor contacts.