Oxide Sub-Fin Gate-All-Around Structures for Sub-10 nm Scaling
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Solution Overview
Problem
The challenge in fabricating integrated circuit structures lies in scaling multi-gate and nanowire transistors below the 10 nanometer node, where maintaining mobility improvement and short channel control becomes difficult due to constraints in lithographic processes.
Innovation Solution
The solution involves fabricating gate-all-around integrated circuit structures with oxide sub-fins, where a thin film oxidation catalyst layer is used to selectively oxidize sub-fin structures, forming oxide sub-fins that improve transistor isolation and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern semiconductor features, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at dimensions below 10 nanometer node
Solution Approach 1:
The patent segments the fin structure into multiple parts: a lower sub-fin structure and an upper fin structure. This segmentation allows different lithographic approaches to be used for different parts, with the sub-fin structure providing a foundation that relaxes the precision requirements for the upper fin structure, thereby improving overall manufacturing precision without proportionally increasing process complexity
Solution Approach 2:
The sub-fin structure is formed in advance before the upper fin structure. This preliminary action creates a pre-positioned foundation that guides subsequent lithographic steps, improving the precision of feature placement while managing process complexity through staged fabrication
2Productivity
If feature size is reduced to increase device density, then productivity is improved, but manufacturing precision deteriorates due to lithographic constraints
Solution Approach 1:
The patent introduces a vertical dimension by creating sub-fin structures at lower elevations. This allows increased device density through vertical stacking while the sub-fin structures provide lithographic reference planes that maintain manufacturing precision even as horizontal feature sizes are reduced
3Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates, then ease of manufacture is improved, but reliability deteriorates due to reduced short channel control
Solution Approach 1:
The patent applies local quality by creating sub-fin structures with specific geometric characteristics at critical locations. These sub-fins provide enhanced gate control locally at the channel region while maintaining compatibility with bulk silicon substrate processing, thus improving reliability without sacrificing ease of manufacture
Solution Approach 2:
The sub-fin structures are nested within or adjacent to the upper fin structures, creating a hierarchical arrangement. This nesting provides enhanced short channel control through the sub-fins while maintaining the overall simplicity of bulk silicon fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved transistor performance by enhancing sub-fin isolation, reducing leakage, and maintaining carrier transport efficiency, while also allowing for more aggressive scaling of transistor dimensions.
Implementation Method 1
oxidizing the sub-fin structure using an oxidation catalyst layer to form an oxide sub-fin structure
Data Source
AI summary
Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.