Oxide TFT Channel Layout for Mask Alignment Tolerance
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Solution Overview
Problem
Variations in mask alignment during the fabrication of oxide semiconductor thin-film transistors (TFTs) lead to inconsistencies in TFT characteristics, affecting the transmittance and reliability of display devices.
Innovation Solution
The oxide semiconductor is formed with a wider channel width than the gate electrode, and the uncovered areas are oxidized to achieve high resistivity, thereby stabilizing TFT characteristics despite variations in mask alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the oxide semiconductor width is made equal to the gate electrode width to maximize pixel transmittance, then the pixel transmittance is improved, but the TFT characteristics vary due to mask alignment inaccuracies
Solution Approach 1:
The oxide semiconductor is designed with non-uniform width: wider in the channel width direction than the gate electrode width to ensure consistent TFT characteristics despite mask alignment variations, while maintaining high pixel transmittance through optimized area arrangement. This local dimensional variation compensates for alignment inaccuracies without sacrificing overall device performance.
2Reliability
If the oxide semiconductor width is increased beyond the gate electrode width to compensate for mask alignment variations, then the TFT characteristic consistency is improved, but the pixel transmittance decreases
Solution Approach 1:
The width parameter of the oxide semiconductor is optimized to be greater than the gate electrode width in the channel width direction. This parameter change creates a tolerance margin that absorbs mask alignment variations, ensuring consistent TFT characteristics while the overall device layout maintains high transmittance efficiency.
3Manufacturing precision
If precise mask alignment is implemented to ensure consistent TFT characteristics, then the manufacturing precision is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The oxide semiconductor is designed with excess width beyond the gate electrode width to create a cushioning effect against mask alignment inaccuracies. This design buffer compensates for manufacturing variations without requiring ultra-precise alignment processes, thereby simplifying the manufacturing process while maintaining product quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the influence of mask alignment variations on TFT characteristics, ensuring consistent performance and increased transmittance in display devices by making the uncovered areas of the oxide semiconductor high resistance, thus enhancing the reliability of the TFTs.
Implementation Method 1
oxidizing a portion of the oxide semiconductor that is not covered by the gate electrode
Data Source
AI summary
The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.