Oxide TFT Array Substrate Layout for Low Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The performance of the active layer in bottom gate homojunction TFTs is affected during the manufacturing of the channel protection layer, and the large parasitic capacitance between the gate and the source/drain due to overlapping areas impacts the TFT's characteristics and stability.
Innovation Solution
A manufacturing method for an array substrate that includes forming a metal oxide semiconductor layer, patterning it to create a source, drain, and active layer, and using a photosensitive material layer to create a channel protection layer without the need for chemical vapor deposition, thereby simplifying the process and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate etching process is used to produce the channel protection layer (PL) made of silicon oxide or silicon nitride, then the active layer is protected, but the process steps become complex and the deposition process affects the oxide active layer performance
Solution Approach 1:
The patent extracts the harmful deposition processes (PECVD, sputtering) from the manufacturing flow and replaces them with a simple coating process for the photosensitive material layer. This eliminates the complex etching steps needed to create inorganic PL layers while avoiding hydrogen introduction and surface damage to the active layer.
Solution Approach 2:
The patent uses a photosensitive material layer (organic polymer) as a disposable channel protection layer instead of permanent inorganic layers. This layer is easily applied, patterned, and removed, replacing complex deposition-based inorganic PL layers with a simple coating-based organic alternative that serves its protective function temporarily during manufacturing.
2Reliability
If the overlapping area between the gate and the source/drain is reduced to decrease parasitic capacitance, then the TFT performance improves, but the alignment between the PL layer and the gate becomes more difficult to control
Solution Approach 1:
The patent inverts the traditional approach by using the gate structure itself as the mask for patterning the channel protection layer, rather than using a separate PL layer as a mask for patterning the gate. This reverse masking approach automatically ensures precise alignment between the gate and the channel protection layer, eliminating alignment errors and enabling better control of the overlapping area to reduce parasitic capacitance.
Solution Approach 2:
The gate structure serves a dual function: as the functional gate electrode and as the masking structure for defining the channel protection layer pattern. This self-service approach eliminates the need for separate alignment processes and ensures automatic precise alignment between the gate and channel protection layer.
3Reliability
If PECVD or sputtering is used to form the channel protection layer, then the active layer is protected, but excessive hydrogen is introduced or surface damage is caused, affecting TFT performance
Solution Approach 1:
The patent replaces permanent inorganic channel protection layers formed by harmful deposition processes with a temporary organic photosensitive material layer. This disposable organic layer is applied by simple coating without introducing hydrogen or causing surface damage, and is removed after serving its protective function during the conductorization treatment.
Solution Approach 2:
The patent substitutes the mechanical/physical deposition processes (PECVD, sputtering) with a chemical coating process for the photosensitive material layer. This replacement eliminates ion bombardment and hydrogen introduction while achieving the same protective function during the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method maintains the performance and stability of the active layer by avoiding processes that can damage it, and reduces parasitic capacitance by minimizing overlapping areas between the gate and the source/drain, leading to improved TFT characteristics and image display quality.
Implementation Method 1
using the first metal layer as a mask to photoetch the photosensitive material layer from the side of the substrate away from the photosensitive material layer
Data Source
AI summary
An array substrate and a manufacturing method therefor, and a display panel are provided. The manufacturing method includes: forming a scan line and a gate on a substrate; forming a first insulating layer covering the scan line and the gate on the substrate; forming a metal oxide semiconductor layer above the first insulating layer, the metal oxide semiconductor layer including a source, a drain and an active layer; coating an upper surface of the metal oxide semiconductor layer with a photosensitive material layer; photoetching the photosensitive material layer from the back side of the substrate by using a first metal layer as a mask to form a channel protection layer; performing conductorization treatment on the metal oxide semiconductor layer to enable the source and the drain to be conductive; forming a data line above the first insulating layer; and forming a pixel electrode above the first insulating layer.