Oxide Semiconductor TFT Layout for OLED Brightness Control
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Solution Overview
Problem
Existing methods for manufacturing OLED display devices struggle to adjust the characteristics of oxide semiconductor transistors, particularly in controlling brightness, due to limitations in etching processes which do not effectively correct defects and optimize transistor performance.
Innovation Solution
A method involving sequential photolithography steps with different mask patterns and exposure doses to shape gate electrodes and insulating layers, along with conductivity providing steps, is used to create transistors with varying resistance regions, allowing for improved control over transistor characteristics and brightness control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional single-step photolithography and etching is used, then manufacturing process is simple, but transistor characteristics cannot be adjusted and brightness control is difficult
Solution Approach 1:
The patent divides the gate electrode formation into multiple photolithography and etching steps, each creating specific resistance regions. The first photolithography step forms a gate electrode conductive film pattern, the second step forms another pattern, and the third step forms a third pattern, allowing different resistance regions to be created in the oxide semiconductor layer, thus enabling transistor characteristic adjustment
Solution Approach 2:
The patent creates local quality variations by forming different resistance regions (first, second, and third resistance regions) in specific areas of the oxide semiconductor layer. Each resistance region has different electrical properties, allowing localized control of current flow and enabling precise adjustment of transistor characteristics for brightness control
2Reliability
If conventional etching process is used, then manufacturing process is straightforward, but etching defects cannot be corrected and wiring short circuits may occur
Solution Approach 1:
The patent performs preliminary actions by forming multiple resist patterns and etching patterns before final transistor operation. The first, second, and third photolithography steps create overlapping patterns that allow defects to be corrected in subsequent steps, ensuring reliable etching results before device operation
Solution Approach 2:
The patent implements feedback by using each etching step's results to guide subsequent photolithography steps. The resist patterns are formed based on previous etching outcomes, allowing defect correction and optimization of the gate electrode structure to prevent wiring short circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables transistors with adjustable characteristics, enhancing brightness control by creating regions with specific resistances, thus improving the performance of OLED display devices.
Implementation Method 1
a first photolithography step of applying a resist to the gate electrode conductive film, and forming, with a first mask, a first resist pattern from the resist
Implementation Method 2
a first gate etching step of etching the gate electrode conductive film with the first resist pattern as a mask
Implementation Method 3
an insulating film etching step of etching the gate insulating film with the first resist pattern as a mask, and shaping the gate insulating film into a gate insulating layer
Implementation Method 4
a conductivity providing step of providing, with the gate insulating layer as a mask, conductivity to a portion of the oxide semiconductor layer outside the first resist pattern
Data Source
AI summary
A display device (1) includes: a substrate (2); and a first transistor (1a) formed on the substrate (2). The first transistor (1a) includes: an oxide semiconductor layer (4) formed on the substrate (2); a gate insulating layer (5) formed on the oxide semiconductor layer (4); and a gate electrode (6) formed on the gate insulating layer (5). The oxide semiconductor layer (4) includes: a conductive region (4a) provided with conductivity; a first resistance region (4b) positioned below the gate electrode (6); and a second resistance region (4c) provided between the conductive region (4a) and the first resistance region (4b), and positioned outside the gate electrode (6). The first resistance (4b) is larger in resistance than the second resistance region (4c).