Oxide Thin-Film Transistor Layout for Reduced Parasitic Capacitance
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Solution Overview
Problem
Thin film transistors using amorphous silicon or polysilicon face limitations in charge mobility and manufacturing complexity, while oxide semiconductors offer higher electron mobility but are prone to parasitic capacitance issues affecting their switching characteristics.
Innovation Solution
A thin film transistor design incorporating an oxide semiconductor with a low conductive region between the source and drain electrodes, an insulating layer covering the semiconductor and low conductive region, and a gate electrode positioned on the insulating layer, which reduces parasitic capacitance and improves carrier concentration gradients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductor is used in thin film transistor, then electron mobility and ON/OFF ratio are improved, but parasitic capacitance increases affecting switching characteristics
Solution Approach 1:
The patent extracts and removes the harmful parasitic capacitance effect by introducing a low conductive region between the source/drain electrodes and the oxide semiconductor channel. This low conductive region acts as a buffer that eliminates the direct capacitive coupling between the electrodes and the semiconductor, thereby removing the harmful parasitic capacitance while preserving the high electron mobility characteristics of the oxide semiconductor.
Solution Approach 2:
The patent introduces a low conductive region as an intermediary layer between the source/drain electrodes and the oxide semiconductor channel. This intermediary region with carrier concentration of 10^16 to 10^18 atoms/cm³ serves as a buffer zone that mediates the interaction between the electrodes and the high-mobility semiconductor, preventing direct parasitic capacitance formation while maintaining electrical connectivity.
2Ease of manufacture
If amorphous silicon is used, then manufacturing process is simplified, but charge mobility is reduced
Solution Approach 1:
The patent employs a composite structure combining oxide semiconductor material with a low conductive region. The oxide semiconductor provides high electron mobility (exceeding 10 cm²/Vs) while the composite structure with the low conductive region maintains manufacturing simplicity by using deposition processes similar to those for amorphous silicon, thereby achieving both ease of manufacture and high charge mobility.
3Reliability
If polysilicon is used, then charge mobility is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent changes the material parameter from polysilicon to oxide semiconductor, which inherently provides high charge mobility (exceeding 10 cm²/Vs) without requiring complex crystallization processes. By adjusting the carrier concentration of the oxide semiconductor and introducing a low conductive region, the patent achieves polysilicon-level mobility with simpler amorphous-phase deposition manufacturing processes.
Data Source
AI summary
A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.