Oxide TFT Fabrication Using Conductive Amorphous Carbon Protective Layer

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Solution Overview

Problem

Current oxide TFT fabrication methods, such as ESL and BCE types, face challenges in complexity, cost, and limited channel size, which restrict the aperture ratio and high PPI applications of display devices.

Innovation Solution

A method involving a conductive amorphous carbon film as a protective layer for the oxide semiconductor, allowing for reduced patterning processes and adjustable channel size through dry etching, eliminating the need for via holes and protecting the oxide semiconductor from etching solutions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an etch stop layer is fabricated on an oxide semiconductor layer, then the oxide semiconductor is well protected, but the fabrication process becomes complicated and cost increases

Engineering Contradiction:
Improveprotection of oxide semiconductorVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A protective layer is introduced as an intermediary between the oxide semiconductor layer and the etching solution. This protective layer serves as a mediator that shields the oxide semiconductor from direct contact with harmful etching solutions, eliminating the need for an etch stop layer while maintaining protection functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts and removes the etch stop layer from the traditional oxide TFT structure, replacing it with a protective layer formed directly on the oxide semiconductor layer. This simplifies the overall structure and reduces the number of fabrication steps while maintaining the essential protection function.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If an etch stop layer is fabricated, then the oxide semiconductor is protected, but the channel size is limited by via hole formation capability

Engineering Contradiction:
Improveprotection of oxide semiconductorVSAvoidchannel size
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The protective layer acts as an intermediary that allows direct formation of source and drain electrodes on the oxide semiconductor layer without requiring via holes through an etch stop layer. This enables the channel size to be determined solely by the source and drain electrode spacing, allowing for smaller channel sizes and higher aperture ratios.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If the patterning process for forming an etch stop layer is omitted, then the fabrication process is simplified, but the oxide semiconductor layer becomes unstable and requires high etching process precision

Engineering Contradiction:
Improvefabrication process complexityVSAvoidstability of oxide semiconductor layer
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The protective layer serves as a dedicated intermediary structure that provides stable protection to the oxide semiconductor layer during etching processes. Unlike omitting the etch stop layer entirely, this protective layer is specifically designed to be removed after serving its protective function, maintaining oxide semiconductor stability while simplifying the overall fabrication process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective layer is formed preliminarily on the oxide semiconductor layer before any etching processes occur. This preliminary protective structure ensures the oxide semiconductor layer remains stable throughout subsequent fabrication steps, and the protective layer is removed only after it has fulfilled its protective purpose.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If via holes are formed to connect source and drain electrodes, then electrical connection is achieved, but the aperture ratio is limited by the distance between via holes

Engineering Contradiction:
Improveelectrical connectionVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts and eliminates the via hole formation step from the fabrication process. By removing the etch stop layer and forming source and drain electrodes directly on the oxide semiconductor layer, the need for via holes is completely eliminated, allowing for minimal spacing between electrodes and maximized aperture ratio.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The protective layer serves as a temporary intermediary that enables direct electrode formation on the oxide semiconductor layer. After the source and drain electrodes are formed with minimal spacing, the protective layer is removed, achieving both reliable electrical connection and maximized aperture ratio without via holes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the fabrication process, increases the aperture ratio, and enhances the application of oxide TFTs in high PPI products by protecting the oxide semiconductor and allowing for adjustable channel sizes.

Implementation Method 1

forming a conductive film that does not react with acid solution on the semiconductor layer to be employed as a protective layer

Methodology Applied
Scientific EffectSelective etching resistance:

Implementation Method 2

removing a portion of the protective layer between the source electrode and the drain electrode by a drying etching process

Methodology Applied
Scientific EffectDry etching:

Data Source

PatentEP3093888B1Method of fabricating a thin film transistor
Publication Date: 2019.12.11 BOE TECHNOLOGY GROUP CO LTD
  • EP3093888B1 patent drawingFigure 1~3
  • EP3093888B1 patent drawingFigure 4~6
  • EP3093888B1 patent drawingFigure 7

AI summary

A thin film transistor, a method of fabricating the same, an array substrate and a display device are disclosed. The method of fabricating the thin film transistor comprises: forming a semiconductor layer; forming a conductive film that does not react with acid solution on the semiconductor layer to be employed as a protective layer; forming a source electrode and a drain electrode on the protective layer; and removing a portion of the protective layer between the source electrode and the drain electrode to expose a portion of the semiconductor layer between the source electrode and the drain electrode.