Layered Oxide Semiconductor TFT Channel for Higher Mobility

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Solution Overview

Problem

Conventional oxide semiconductor TFTs, particularly those with a top-gate structure, face challenges in achieving sufficient channel mobility due to the physical properties of oxide semiconductors, which also results in lower channel mobility when attempting to reduce parasitic capacitance.

Innovation Solution

The proposed solution involves a thin film transistor with a layered structure in its active layer, comprising a lower oxide semiconductor layer, a first metal layer with no oxygen, and an upper oxide semiconductor layer. This configuration enhances channel mobility while maintaining a high OFF characteristic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the overlap length between gate and source/drain is reduced to decrease parasitic capacitance, then parasitic capacitance is reduced, but channel mobility is further lowered

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidchannel mobility
Core Design Contradiction:
Loss of energyVSSpeed

Solution Approach 1:

The active layer is segmented into multiple functional regions: a channel formation region with high carrier concentration for mobility, source/drain regions with even higher carrier concentration for low resistance, and intermediate regions for transition. This segmentation allows optimization of each region's properties independently, maintaining high channel mobility while managing parasitic capacitance through proper spatial distribution of functions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the active layer are given different local properties through selective doping or material composition. The channel region has optimized carrier concentration for mobility, while source/drain regions have higher doping for electrical connection. This local quality differentiation resolves the contradiction by allowing the gate overlap structure to be optimized for capacitance reduction while the channel region maintains high mobility through its specific local properties.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If conventional oxide semiconductor TFT structure is used, then manufacturing is simplified, but sufficient channel mobility cannot be realized due to physical properties of oxide semiconductor

Engineering Contradiction:
Improvestructure simplicityVSAvoidchannel mobility
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The active layer uses a composite structure combining oxide semiconductor material with controlled doping elements or compound compositions. This composite approach maintains the manufacturability of oxide semiconductor TFTs while enhancing channel mobility through the specific properties of the composite material system, such as improved carrier concentration and mobility characteristics.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The physical parameters of the oxide semiconductor are changed through controlled doping, stoichiometry adjustment, or crystalline structure modification. These parameter changes enhance the inherent mobility limitations of oxide semiconductors while maintaining compatibility with conventional manufacturing processes, thus resolving the contradiction between ease of manufacture and achievable channel mobility.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12224356B2Thin film transistor and manufacturing method of same, and display device
Publication Date: 2025.02.11 SAKAI DISPLAY PROD
  • US12224356B2 patent drawing
  • US12224356B2 patent drawing
  • US12224356B2 patent drawing

AI summary

A thin film transistor 101 includes: an active layer 7 that is supported on a substrate 1 and includes a first region 7S, a second region 7D and a channel region 7C located between the first region and the second region; a gate electrode 11 that is arranged so as to overlap with at least the channel region of the active layer 7 with a gate insulating layer 9 therebetween; a source electrode 15s electrically connected to the first region 7S; and a drain electrode 15d electrically connected to the second region 7D, at least the channel region 7C of the active layer 7 having a layered structure that includes a first metal layer m1 arranged on a lower oxide semiconductor layer 71 and containing substantially no oxygen, and an upper oxide semiconductor layer 72 arranged on the first metal layer m1, wherein a thickness of the first metal layer m1 is smaller than a thickness of the lower oxide semiconductor layer 71 or the upper oxide semiconductor 72.