Overlapped Poly-Si and Oxide TFT CMOS Layout for Faster Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CMOS circuits incorporating low-temperature polysilicon TFTs and oxide semiconductor TFTs face challenges in manufacturing time, cost, and circuit area, with overlapping transistors contributing to high gate capacitance and slow switching responses.
Innovation Solution
A CMOS circuit design that integrates p-channel transistors with polycrystalline silicon layers and n-channel transistors with oxide semiconductor layers, allowing them to overlap and share gates, reducing the need for impurity injection masks and processing steps, thereby minimizing manufacturing time and cost while decreasing circuit area and gate capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If low-temperature polysilicon TFT and oxide semiconductor TFT are incorporated in a single circuit, then device functionality is improved, but manufacturing time and cost increase due to additional processing steps
Solution Approach 1:
The patent merges the manufacturing processes for low-temperature polysilicon TFTs and oxide semiconductor TFTs by forming both transistor types using the same impurity injection masks. The masks are used to define source and drain regions for both transistor types simultaneously, eliminating the need for separate masking steps and reducing overall manufacturing time while maintaining device functionality
Solution Approach 2:
The impurity injection masks serve multiple functions: they define source and drain regions for both low-temperature polysilicon TFTs and oxide semiconductor TFTs, and they establish the spatial relationship between the two transistor types. This multi-functional use of single masks reduces the total number of processing steps required
2Adaptability or versatility
If low-temperature polysilicon TFT and oxide semiconductor TFT are incorporated in a single circuit, then device functionality is improved, but manufacturing cost increases due to additional processing steps
Solution Approach 1:
The patent combines the manufacturing processes for both transistor types into a single integrated process flow. By using the same impurity injection masks for both low-temperature polysilicon TFTs and oxide semiconductor TFTs, the number of separate processing steps is reduced, directly lowering manufacturing costs while preserving device functionality
Solution Approach 2:
The patent eliminates redundant processing steps by discarding the conventional approach of using separate masks for each transistor type. Instead, it recovers efficiency by using a unified masking strategy that serves both transistor types, reducing material waste and processing complexity
3Area of stationary object
If transistors are configured to overlap, then circuit area is reduced, but gate capacitance increases leading to slow switching responses
Solution Approach 1:
The patent applies local quality by strategically positioning oxide semiconductor TFTs in overlapping regions with low-temperature polysilicon TFTs only where it reduces circuit area without significantly increasing gate capacitance. The overlapping configuration is optimized to maintain fast switching responses in critical circuit paths while achieving compact layout
Data Source
AI summary
According to one embodiment, a CMOS circuit includes a p-channel type transistor including a polycrystalline silicon layer and an n-channel type transistor including an oxide semiconductor layer, and the p-channel transistor and the n-channel transistor are complementarily connected to each other, and the polycrystalline silicon layer and the oxide semiconductor layer overlap each other in plan view.